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API-first AI Automation Advanced Analytics B2B Infrastructure Payment Networks Gateways Integration Platforms Migration Strategies Portfolio Management Data Science Network Services +7 more Show less

SIEM SOAR Log Management AI Data Analysis CQL LogScale Detection Engineering Cybersecurity Cloud Security Identity Protection Exposure Management Content-as-Code Data Ingestion Threat Hunting +10 more Show less

HPC C++ Python SystemC TLM Performance Analysis Benchmarking PCIe CXL InfiniBand RoCE Silicon Validation Cache and Memory Subsystems Profiling Simulation Environments +10 more Show less

HPC C++ Python SystemC TLM Performance Analysis Benchmarking PCIe CXL InfiniBand RoCE Silicon Validation Cache and Memory Subsystems Profiling Simulation Environments +10 more Show less

Java C++ Rust Low Latency CI/CD Agile SDLC High-Throughput Architecture Concurrency Automated Testing Electronic Trading Market Data Processing Smart Order Routing DMA Performance Optimization +10 more Show less

ASIC Design RTL Design SystemVerilog Verilog Computer Architecture Synopsys Synthesis Low Power Design Python C++ C Coverage-based Design Verification SoC Interconnects Memory Controllers micro architecture Debugging +10 more Show less

ASIC Design RTL LPDDR HBM DDR NoC SRAM Cache Controller x86 ARM Synthesis Timing Closure Gate Level Simulation Power Analysis Physical Design Micro-architecture ISA +12 more Show less

Bioinformatics DNA-seq RNA-seq Proteomics Long-read sequencing Base calling Read mapping Variant calling Multi-omics PacBio Illumina Olink Ultima NVIDIA Google Brain Data Structures +11 more Show less

RTL Verilog SystemVerilog C/C++ SystemC Python Perl Unix Linux Shell Scripting DSP 4G 5G 3GPP ML Generative AI Synthesis LINT Clock Domain Crossing Low Power Design +15 more Show less

Statistics Operations Research Computer Science Information Systems Business Strategy Digital Products +1 more Show less

ASIC RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Design Verification Scripting Logic Design +4 more Show less

Verilog SystemVerilog C++ C RTL Design Microarchitecture Power Management Clock Domain Crossing CDC Analysis Firmware DVFS Silicon Validation Design-for-Debug Design-for-Test Digital Design +10 more Show less

Program Management Risk Management Scope Management Schedule Management Metrics Technical Judgment Computer Science +2 more Show less

ASIC Design RTL Coding Hardware Architecture LPDDR HBM NoC SRAM Cache Controller x86 ARM Synthesis Timing Closure Physical Design Gate Level Simulation Power Analysis Digital Design ISA Architecture +12 more Show less

ASIC Design RTL Coding Front-end Digital Design Hardware Architecture LPDDR HBM SRAM Cache Controller NoC x86 ARM Synthesis Timing Closure Gate Level Simulation Power Analysis ISA Architecture +11 more Show less

SystemVerilog UVM OVM Python C++ Verilog VHDL SystemC Perl Linux Unix Formal Verification DSP 3GPP ML GenAI Makefiles XML RTL Design +14 more Show less

RTL Verilog SystemVerilog C/C++ SystemC Python Perl Unix Linux Shell Scripting DSP 3GPP 4G 5G ML Generative AI Synthesis LINT Makefiles XML +15 more Show less

Verilog SystemVerilog ASIC Design RTL Design Synopsys Synthesis Low Power Design Python C C++ Computer Architecture Coverage-based Design Verification SOC Interconnects Memory Controllers micro architecture +9 more Show less

Aerodynamics Structures GNC Propulsion Avionics Software SIL HIL System Integration DFM DFA Additive Manufacturing Advanced Composites Root Cause Analysis +9 more Show less

AI ML 3D CG Animation Unreal Engine MetaHuman Maya Computer Graphics Algorithm Development R&D Simulation Visualization +6 more Show less