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Verilog VHDL SystemVerilog SOC Architecture DRAM Interface Design Synthesis Formal Verification Timing Closure Signal Integrity Physical Implementation HDL +6 more Show less

Physical Design Place and Route Static Timing Analysis Physical Verification Formal Equivalency Verification IR-Drop Electromigration TCL Python Synopsys Fusion Compiler PrimeClosure Primetime Formality VCLP Star-RC Redhawk SC Cadence Innovus Siemens Calibre ASIC SOC +15 more Show less

Verilog SystemVerilog RTL Design SoC PCIe HBM AMBA AXI DMA Synthesis Timing Constraints CDC Lint RDC DFT Python Perl Agile Post-Silicon Debug +13 more Show less

NX SolidWorks Creo Teamcenter ASME Y14.5 GD&T FEA Abaqus ANSYS CAD PLM PDM DFM DFA CNC Machining Injection Molding Thermal Management +12 more Show less

ASIC Design RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Verification Scripting SoC Circuit Design +5 more Show less

SolidWorks NX Creo Teamcenter ASME Y14.5 GD&T FEA CAD PLM PDM DFM DFA 3/5-axis CNC Machining Injection Molding Thermal Management RF/EMI Shielding SOPs +12 more Show less

RTL Verilog System Verilog ASIC SoC Microarchitecture Synthesis Clock Domain Crossing Lint PPA Post-Silicon Debug Network on Chip Digital Design +8 more Show less

ASIC RTL SoC ARM DDR UCIe Ethernet AMBA DFT STA Synthesis Lint CDC PPA silicon bring up ATE Logic Design +12 more Show less

RTL Design AMBA Computer Architecture Synthesis Static Timing Analysis Clock Domain Crossing DFT BIST Power Intent Formal Verification ASIC Design +6 more Show less

RTL AMBA Computer Architecture Synthesis Static Timing Analysis Clock Domain Crossing DFT BIST Power Intent Formal Verification ASIC Design +6 more Show less

RTL Verilog Python ASIC DFT Logic Synthesis PPA Silicon Debug Timing Closure Power Optimization Cross-talk OCV Scripting +8 more Show less

RTL Verilog VHDL Python Perl Microarchitecture Logic Design Functional Verification Waveform Debugging Instruction Fetch Branch Prediction +6 more Show less

PCB Design SoC Architecture Signal Integrity Power Integrity Cadence OrCAD Allegro PCIe LPDDR5 FPGA HDI IC Packaging EDA Tools ANSYS Siemens EDA PMICs +10 more Show less

Verilog System Verilog RTL ASIC Design SoC Digital Signal Processing Synthesis Power-Gating AMBA AXI AHB APB Python Perl TCL Linting CDC RDC +13 more Show less

Verilog System Verilog RTL ASIC SoC Digital Signal Processing AMBA AXI AHB APB Python Perl TCL Synthesis power-gating CDC RDC +12 more Show less

Verilog System Verilog RTL ASIC Design Digital Signal Processing AMBA AXI AHB APB Synthesis Python Perl TCL SystemC C++ Finite State Machines Pipelining High-Level Synthesis +13 more Show less

Human-Centered Design Information Architecture UX) Research Prototyping ReactJS JavaScript CSS HTML Tailwind Figma Jira Confluence Agile SAFe Section 508 User Testing +11 more Show less

Human-Centered Design UX Research Information Architecture Interaction Design Prototyping Design Systems Agile AI data, analytics Risk Management Trading Systems Accessibility +7 more Show less

3D Memory ASIC Design RTL Verilog Verilog-A Verilog-AMS C C++ Python Perl Matlab EDA Tools HBM3/4 LPDDR PCIe UCIe UAL SRAM DRAM FLASH 2.5D/3D Integration +16 more Show less

Quantum Engineering Readout Circuitry Semiconductor Devices Cryogenic Microwave Experiments Low-Noise Amplifiers Simulation Artificial Intelligence Performance Modeling Hardware Development +4 more Show less