Intern, Hardware ASIC Design

Nvidia

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Quick summary

Work type
On-site
Location
Santa Clara, CA
Employment
Full-time
Posted
46 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

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Salary context

How this pay compares to similar roles

Similar $190k
$141k most similar roles pay here $240k

This listing doesn't post a salary. Most similar roles pay $162,000–$218,950.

Based on 240 similar postings.

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About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1391 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1116 roles with salary data.

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At a glance

TL;DR · Intern, Hardware ASIC Design

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NVIDIA 2027 Internships: Hardware ASIC Design is a full-time internship within the Hardware team where students will work on projects that have a measurable impact on the business. The role focuses on hardware design and development, requiring candidates to engage with technical challenges in accelerated computing. Candidates must be pursuing a B.S., M.S., or Ph.D. in Electrical Engineering, Computer Engineering, or related fields. Key responsibilities and required knowledge areas include RTL Design and HDL, Digital Systems, VLSI Design, Timing and Static Timing Analysis, Synthesis, Power and Performance Optimization, Testbench Creation, Gate-Level Netlist, Computer Architecture, and System-on-Chip design. Relevant technical skills and tools include SystemVerilog, Verilog, VHDL, UVM, Perl, TCL, C, C++, Python, Linux, and various testbench tools to support the development of advanced hardware components and integrated circuits.

Skills

RTL Design HDL SystemVerilog Verilog VHDL UVM Digital Design VLSI Design STA Synthesis Testbench Creation Computer Architecture SoC SRAM Design Physical Design Timing Closure Python C++ TCL Perl Linux

What you'll do

  • Design and implement RTL logic using HDL languages like Verilog, SystemVerilog, or VHDL.
  • Perform timing and static timing analysis (STA) to ensure circuit performance.
  • Optimize power and performance for integrated circuits and SoC designs.
  • Create testbenches and develop verification methodologies to ensure design functionality.
  • Conduct synthesis and gate-level netlist analysis for hardware components.
  • Develop CAD tools and physical design flows, including floorplanning and P&R.
  • Analyze architectural tradeoffs and perform power/noise analysis on silicon designs.
  • Utilize scripting languages like Python, Perl, or TCL to automate design workflows.

What we're looking for

  • Must be actively enrolled in a university pursuing a B.S., M.S., or Ph.D. degree in Electrical Engineering, Computer Engineering, or a related field.
  • Resume must clearly indicate the anticipated graduation date (month and year).
  • Experience or knowledge in RTL Design, HDL, Digital Systems, VLSI Design, or Chip Blueprint is required.
  • Knowledge of Timing and Static Timing Analysis (STA), Synthesis, Power and Performance Optimization, or Testbench Creation may be required.
  • Familiarity with Computer Architecture, Circuit Design, System-on-Chip (SoC), or SRAM Design may be required.
  • Experience in CAD and Physical Design Methodologies, Floorplanning, or Packaging may be required.
  • Proficiency in programming languages such as SystemVerilog, Verilog, VHDL, UVM, Perl, TCL, C, C++, Python, or Linux may be required.

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