Principal Design Verification Engineer

Microsoft

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Hybrid

Quick summary

Work type: Hybrid
Location: —
Salary: $142,800–$274,800 / yr
Posted: 14 days ago
Freshness: Confirmed live today
Closes: Apr 11, 2027

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $205k

This role $209k

$127k $291k

below market most similar roles pay here above market

This role pays more than 59% of similar roles. Most pay $177,200–$233,312 — the blue band above. At the midpoint, this role pays about $209k versus about $205k for comparable roles.

Based on 240 similar postings.

Employer

About Microsoft

Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing

Microsoft currently has 694 open roles on FindRole.

Listed pay typically runs $119,800–$234,700 across 651 roles with salary data.

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At a glance

TL;DR · Principal Design Verification Engineer

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The Principal Design Verification Engineer joins the AI Silicon Engineering SoC Design Verification team to verify Microsoft’s latest AI accelerators. This role involves creating complex verification environments and tests for pre-silicon functional verification at the block, chip, and system levels, as well as reference modeling and post-silicon validation. You will develop verification components like scoreboards, sequences, constraints, assertions, and functional coverage while triaging and debugging testbench, simulation, and emulation fails. Key technologies include UVM, SystemVerilog, C++, and scripting languages like Python, Ruby, or Perl. You will also utilize agentic DV workflows such as Co-Pilot and apply Agile methodologies. The work focuses on solving complex quality and design challenges for AI silicon, requiring collaboration with architects and design engineers to ensure complete feature coverage.

What does a Design Verification Engineer earn?

Median $189224 from 84 postings across 10 companies.

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Skills

SystemVerilog UVM C++ Python Verilog VHDL Ruby Perl Agile Hardware Emulation FPGA Makefiles Scripting Post-Silicon Validation Pre-Silicon Functional Verification

What you'll do

Create complex verification environments and tests using UVM, SystemVerilog, and C++.
Develop verification plans covering strategy, test environments, and requirements for IP and SoC levels.
Drive test development to ensure complete feature coverage for AI accelerators.
Implement technical solutions for complex quality and design challenges.
Develop verification components including scoreboards, sequences, constraints, assertions, and functional coverage.
Triage and debug testbench, simulation, and emulation failures.
Develop Makefiles and scripts to ensure scalable and efficient verification processes.
Adopt agentic DV workflows and the latest AI methodologies like Co-Pilot.

What we're looking for

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience.
Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience.
Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience.
Equivalent experience to the above degree and years of experience requirements.
Ability to pass the Microsoft Cloud background check.
Must provide proof of citizenship, US residency, or other protected status for export control regulations.
9+ years of experience in creating simulation environments, developing tests, and debugging for multiple silicon IPs or systems (preferred).
5+ years of industry experience in Verilog/VHDL, C/C++, and scripting languages like Python, Ruby, or Perl (preferred).