Hardware Design for Test (DFT) Intern

Nvidia

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Quick summary

Work type: On-site
Location: Santa Clara, CA
Employment: Full-time
Posted: 46 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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Similar $191k

$140k most similar roles pay here $237k

This listing doesn't post a salary. Most similar roles pay $155,300–$227,350.

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About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1391 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1116 roles with salary data.

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At a glance

TL;DR · Hardware Design for Test (DFT) Intern

Role Posting Log in to save

NVIDIA 2027 Internships: Hardware Design for Test (DFT) is a technical internship role within the hardware team focused on critical chip testing and architecture. During this twelve-week full-time internship, you will work on projects with measurable business impact involving design for test, digital design, test architecture, and DFT planning. Your daily responsibilities involve tasks such as static timing analysis, pre-silicon and post-silicon issue debug scan chain design, ATPG, boundary scan, JTA, memory BIST, logic BIST, and compression techniques like EDT or streaming scan networks. You will also perform at-speed and delay testing to verify chip frequencies. The role requires proficiency in tools and languages including Perl, TCL, C, C++, Python, Synopsys, TetraMAX, Cadence Modus, and Linux. This position addresses complex hardware engineering challenges within the domain of accelerated computing and semiconductor design.

Skills

Design for Test (DFT) Digital Design Static Timing Analysis (STA) Scan Chain Design ATPG Boundary Scan JTA Memory BIST Logic BIST Compression Perl TCL C C++ Python Synopsys TetraMAX Cadence Modus Linux

What you'll do

Execute Design for Test (DFT) tasks to ensure chip manufacturability and testability.
Perform Static Timing Analysis (STA) to verify timing constraints of digital designs.
Develop and design scan chains for pre-silicon and post-silicon issue debugging.
Implement Automatic Test Pattern Generation (ATPG) for circuit testing.
Design and implement Memory BIST and Logic BIST with compression techniques.
Conduct at-speed and delay testing to verify chip performance at rated frequencies.
Utilize tools like Synopsys, TetraMAX, or Cadence Modus for hardware design tasks.
Develop scripts using Python, Perl, or TCL to automate design and test workflows.

What we're looking for

Must be actively enrolled in a university pursuing an M.S. or Ph.D. degree in Electrical Engineering, Computer Engineering, or a related field.
Resume must clearly indicate the anticipated graduation date (month and year).
Experience or coursework in Design for Test (DFT), Digital Design, Test Architecture, or DFT Planning is required.
Experience or knowledge in Static Timing Analysis (STA) may be required.
Experience or knowledge in Pre-Silicon/Post-Silicon Issue Debug Scan Chain Design and ATPG may be required.
Experience or knowledge in Boundary Scan, JTA, Memory BIST, Logic BIST, and Compression may be required.
Experience or knowledge in At-Speed and Delay Testing may be required.
Proficiency in Perl, TCL, C, C++, Python, Synopsys, TetraMAX, Cadence Modus, or Linux may be required.

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