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UVM Formal Verification Python PCIe CXL AMBA CHI Fabric Interconnects Assertions Coverage Simulation Data Analysis Automation AI-driven solutions +9 more Show less

SystemVerilog UVM Constrained-Random Verification Coverage-Driven Verification Python Perl Shell ASIC Verification RTL CHI AXI FPGA Emulation Coherent Interconnects +9 more Show less

System Verilog UVM Python PCIe CXL CHI AMBA Generative AI Fabric Interconnects Coherency Simulation Test Bench IP Verification Post-processing +9 more Show less

System Verilog UVM Python PCIe CXL CHI AMBA Generative AI Fabric Interconnects SOC Simulation Verification Environments Post-processing +8 more Show less

Semiconductor Fabrication Quantum Transduction Single-Photon Detection Quantum Memory Cryogenic Characterization Heterogeneous Integration Materials Engineering Device Design Process Engineering +4 more Show less

SerDes PAM4 Signal Integrity Power Integrity PCB Design Advanced Packaging ADS HFSS CST HSPICE MATLAB Python Cadence Sigrity PowerSI Clarity SystemVerilog Verilog-A IBIS-AMI Ethernet PCIe NVLink UCIe FEC +18 more Show less

System Verilog UVM RTL Design Python Perl Formal Verification AMBA AXI ACE CHI Microarchitecture Cache Coherence Data Structures Algorithms Object-Oriented Programming +10 more Show less

Electrical Engineering Ethernet EtherCAT CAN RS-232/485 USB Python Matlab EMI/EMC Signal Integrity SECS/GEM SolidWorks Electrical EPLAN Zuken Oscilloscopes Protocol Analyzers DOE Data Analysis +13 more Show less

SystemVerilog UVM RTL Design Formal Verification Python Perl AMBA CHI PCIe Compute Express Link Cache Coherence Memory Systems Bus Protocols +7 more Show less

SystemVerilog UVM RTL Design Formal Verification Python Perl AMBA CHI PCIe Compute Express Link Cache Coherence Memory Systems Bus Protocols +7 more Show less

Signal Integrity HFSS PCB Design RF VNA Network Analyzers Mixed-Signal Materials Modeling Lab Characterization +4 more Show less

SystemVerilog UVM Unix Perl Git UPF Gate-level Simulation Formal Verification LPDDR SoC +5 more Show less

Verilog SystemVerilog RTL PCIe CXL UCIe SoC Microarchitecture Python Tcl Perl AXI ACE CHI APB IP-XACT NoC AI/ML Agentic AI Chiplet +15 more Show less

Physical Design ASIC Design Flow Synthesis Timing Analysis Verilog RTL Design DFT ECO Floor-planning High-Frequency Design Micro-architecture +6 more Show less

Verilog System Verilog RTL Design PCIe CXL AXI CHI SerDes DDR LPDDR Link Layer Physical Layer Performance Analysis Power Optimization Chiplets +10 more Show less

Optical Interconnects SerDes PAM4 400G 800G 1.6T Signal Integrity Power Integrity Python ASIC CMIS MSA I2C FEC BER Testing DCA-X BERT Real-time Oscilloscopes Optical Spectrum Analyzers Silicon Photonics Co-packaged Optics Hardware Validation +17 more Show less

SystemVerilog UVM Verilog C C++ SystemC TLM ASIC Verification RTL Constrained-Random Verification Code Coverage Perl Ruby Makefiles HLS Linux Windows +12 more Show less