Design Verification Engineer, Infinity Fabric and Chiplet Interconnect

Amd

Confirmed live today High trust

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $200,000–$300,000 / yr
Posted: 152 days ago
Freshness: Confirmed live today
Closes: May 28, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $202k

This role $250k

$132k $318k

below market most similar roles pay here above market

This role pays more than 86% of similar roles. Most pay $169,625–$233,950 — the blue band above. At the midpoint, this role pays about $250k versus about $202k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 496 open roles on FindRole.

Listed pay typically runs $172,000–$258,000 across 496 roles with salary data.

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At a glance

TL;DR · Design Verification Engineer, Infinity Fabric and Chiplet Interconnect

Role Posting Log in to save

JOB TITLE: Design Verification Engineer, Infinity Fabric and Chiplet Interconnect The Design Verification Engineer joins the Infinity Fabric transport layer verification team to verify advanced interconnect technology used across Client, Server, Graphics, and Semi-Custom products. The role involves defining and executing verification strategies for configurable switches, transport-layer features, and die-to-die connectivity. Key responsibilities include owning verification planning, developing scalable environments, and debugging complex interactions across testbenches, RTL, and firmware. The candidate will utilize SystemVerilog, UVM, Verilog, C, C++, SystemC, and TLM to build directed and constrained-random testing environments. Technical skills in Perl, Ruby, Makefiles, and shell scripting are also required. This position solves complex technical challenges in processor architecture and digital design, focusing on functional and code coverage closure for highly configurable digital designs and subsystems.

What does a Design Verification Engineer earn in California?

Median $199500 from 57 postings across 7 companies.

See salary data

Skills

SystemVerilog UVM Verilog C C++ SystemC TLM ASIC Verification RTL Constrained-Random Verification Code Coverage Perl Ruby Makefiles HLS Linux Windows

What you'll do

Define and execute verification strategies for complex Infinity Fabric features and subsystems.
Develop robust, scalable verification environments using SystemVerilog and UVM.
Own verification planning for critical areas by identifying risks and developing mitigation strategies.
Debug complex interactions across testbenches, RTL, firmware, and architectural models.
Analyze functional and code coverage to drive coverage closure strategies.
Improve verification processes, tools, automation, and workflows to increase productivity.
Solve ambiguous verification challenges by developing new approaches or extending existing methodologies.

What we're looking for

BS or MS degree in Electrical Engineering, Computer Engineering, or Computer Science (preferred).
Proficiency in IP-level ASIC verification (preferred).
Hands-on experience with UVM concepts, testbenches, and SystemVerilog (preferred).
Experience with Verilog, SystemVerilog, C, and C++ (preferred).
Experience developing directed and constrained-random verification environments (preferred).
Experience with functional and code coverage analysis and coverage closure (preferred).
Scripting experience with Perl, Ruby, Makefiles, shell, or similar languages (preferred).
Experience working in Linux and Windows environments (preferred).

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