Senior RTL Engineer, IO Die and Interconnect IP

Samsung Semiconductor

Confirmed live 2 days ago High trust

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$138,000–$206,000 / yr
Posted
21 days ago
Freshness
Confirmed live 2 days ago
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $196k
This role $172k
$126k most similar roles pay here $246k

This role pays less than 77% of similar roles. Most pay $176,687–$216,250 — the shaded band above. At the midpoint, this role pays about $172k versus about $196k for comparable roles.

Based on 240 similar postings.

Employer

About Samsung Semiconductor

Samsung Semiconductor is the global semiconductor business unit of Samsung Electronics, designing and manufacturing memory chips, logic semiconductors, and foundry solutions for a broad range of applications.

Samsung Semiconductor currently has 49 open roles on FindRole.

Listed pay typically runs $163,000–$253,000 across 49 roles with salary data.

Most-posted roles

View all roles at Samsung Semiconductor

At a glance

TL;DR · Senior RTL Engineer, IO Die and Interconnect IP

Role Posting Log in to save

As a Senior RTL Engineer, IO Die and Interconnect IP within the AGI Computing Lab, you will develop Verilog and SystemVerilog for an IO die to integrate UCIe, PCIe, CXL, and NoC into a cohesive chiplet-based architecture. You will be responsible for microarchitecture and RTL for IO subsystems, including controllers, adapters, and fabric bridges, while customizing third-party IP to meet specific requirements. The role involves managing trade-offs between performance, power, area, and latency while collaborating with verification, physical design, and software teams. You will utilize scripting languages like Tcl, Python, or Perl, along with agentic AI tools, to automate integration flows. This position addresses the complex system-level challenges of high-demand AI/ML workloads by designing scalable platforms that optimize computational performance and memory requirements while minimizing energy consumption in advanced computing environments.

Skills

Verilog SystemVerilog RTL Design UCIe PCIe CXL NoC SoC Integration IP-XACT AXI ACE CHI APB Python Tcl Perl AI/ML Agentic AI

What you'll do

  • Develop RTL using Verilog and SystemVerilog for the IO die and chiplet-based architectures.
  • Integrate internal and third-party interconnect IPs including UCIe, PCIe, CXL, and NoC into the IO die.
  • Modify and customize PCIe and other interconnect IP to meet specific die-level requirements.
  • Define and implement die-to-die and chiplet interfaces while ensuring protocol compliance and interoperability.
  • Own the microarchitecture and RTL for IO subsystems such as controllers and fabric bridges.
  • Collaborate with verification engineers to develop test plans and debug functional issues at the IP and subsystem levels.
  • Make design decisions regarding trade-offs between performance, power, area, latency, bandwidth, and cost.
  • Automate IP integration and RTL assembly flows using scripting and agentic AI tools.

What we're looking for

  • Bachelor’s with 5+ years, Master’s with 3+ years, or PhD with 0+ years of experience.
  • Strong background in microarchitecture and RTL design for complex SoC and die integration.
  • 5+ years of experience in RTL development using Verilog/SystemVerilog for high-speed interconnect and IO subsystems.
  • Hands-on experience integrating and configuring PCIe, CXL, UCIe, and die-to-die interfaces.
  • Experience modifying or customizing third-party interconnect IP to meet specific die-level requirements.
  • Solid understanding of PCIe/CXL protocol stacks and the PIPE interface.
  • Experience with SoC integration methodologies, IP packaging (e.g., IP-XACT), and on-chip protocols like AXI, ACE, CHI, or APB.
  • Proficiency in scripting (Tcl, Python, or Perl) for design automation; familiarity with agentic AI tools is preferred.

Related searches

More Senior RTL Engineer jobs Senior RTL Engineer jobs in San Jose All jobs at Samsung Semiconductor

More like this

Similar roles

Senior RTL Engineer, Memory Centric Computing

Samsung Semiconductor

San Jose, CA 23 days ago $138,000–$206,000
Verilog System Verilog HLS RTL Microarchitecture Computer Architecture Memory Controller NoC Interconnect IP SoC Integration AI/ML Pipelining Data Compression
5+ yrs exp
Save

Integration RTL Design Engineer

Amd

San Jose, CA 169 days ago $166,400–$249,600
Verilog RTL Design ASIC SoC STA SDC PrimeTime Tempus AMBA AXI AHB APB PCIe CXL Python Perl Tcl DFT Low-Power Design
Hybrid
Save

CPU Core RTL Design Engineer

Amd

Austin, TX 65 days ago $178,400–$267,600
Verilog SystemVerilog RTL Design CPU Architecture ASIC SoC Logic Design Synthesis Timing Closure Python Tcl DFT Power Management Post-silicon Debug Place-and-Route
Hybrid
Save

Senior RTL Design Engineer, Silicon Engineering

SpaceX

Palo Alto, CA 113 days ago $175,000–$280,000
Verilog System Verilog ASIC SoC RTL Design Python AXI AHB HDL Simulators EDA Tools Timing Closure Synthesis Clock Domain Crossing Power Optimization Silicon Bring-up
5+ yrs exp
Save

Senior RTL Design Engineer

SpaceX

Irvine, CA 113 days ago $165,000–$260,000
Verilog System Verilog ASIC SoC RTL Design Python AXI AHB Synthesis Timing Closure HDL Simulators EDA Tools Clock Domain Crossing Power Optimization Silicon Bring-up
5+ yrs exp
Save