Senior RTL Engineer, IO Die and Interconnect IP

Samsung Semiconductor

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$138,000–$206,000 / yr
Posted
67 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $195k
This role $172k
$126k $246k
below market most similar roles pay here above market

This role pays less than 74% of similar roles. Most pay $172,000–$217,525 — the blue band above. At the midpoint, this role pays about $172k versus about $195k for comparable roles.

Based on 240 similar postings.

Employer

About Samsung Semiconductor

Samsung Semiconductor is the global semiconductor business unit of Samsung Electronics, designing and manufacturing memory chips, logic semiconductors, and foundry solutions for a broad range of applications.

Samsung Semiconductor currently has 36 open roles on FindRole.

Listed pay typically runs $163,000–$253,000 across 36 roles with salary data.

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At a glance

TL;DR · Senior RTL Engineer, IO Die and Interconnect IP

Role Posting Log in to save

The Senior RTL Engineer joins the AGI Computing Lab to develop RTL for the IO die, integrating high-speed interconnect IP into a chiplet-based architecture. The role involves developing Verilog and SystemVerilog for the IO die, integrating internal and third-party interconnects like UCIe, PCIe, CXL, and NoC. Key responsibilities include owning the microarchitecture and RTL for IO subsystems, customizing PCIe controllers, and implementing die-to-die interfaces to ensure protocol compliance. The engineer will collaborate with verification, architecture, and physical design teams to balance performance, power, latency, and bandwidth. Required skills include experience with PCIe/CXL protocol stacks, AXI, ACE, CHI, and APB protocols, along with proficiency in Tcl, Python, or Perl scripting. This role addresses complex system-level challenges for AI/ML workloads by designing scalable, energy-efficient computing platforms.

Skills

Verilog SystemVerilog RTL PCIe CXL UCIe SoC Microarchitecture Python Tcl Perl AXI ACE CHI APB IP-XACT NoC AI/ML Agentic AI Chiplet

What you'll do

  • Develop RTL using Verilog or SystemVerilog for the IO die and chiplet-based architecture.
  • Integrate internal and third-party interconnect IPs including UCIe, PCIe, CXL, and NoC.
  • Customize PCIe and other interconnect IP to meet specific die-level functional requirements.
  • Define and implement die-to-die interfaces to ensure protocol compliance and interoperability.
  • Own the microarchitecture and RTL for IO subsystems like PCIe/CXL controllers and fabric bridges.
  • Develop and automate IP integration and RTL assembly flows using scripting and agentic AI tools.
  • Collaborate with verification engineers to develop test plans and debug functional issues at the IP and die levels.
  • Make design decisions regarding trade-offs between performance, power, latency, bandwidth, and cost.

What we're looking for

  • Bachelor’s with 5+ years, Master’s with 3+ years, or PhD with 0+ years of industry experience.
  • Strong background in microarchitecture and RTL design for complex SoC and die integration.
  • 5+ years of experience in RTL development using Verilog/SystemVerilog for high-speed interconnect and IO subsystems.
  • Hands-on experience integrating and configuring interconnect IP such as PCIe, CXL, UCIe, and die-to-die interfaces.
  • Experience modifying or customizing third-party interconnect IP to meet die-level requirements.
  • Solid understanding of PCIe/CXL protocol stacks and on-chip interface protocols such as AXI, ACE, CHI, or APB.
  • Proficiency in scripting (Tcl, Python, or Perl) for design integration and automation; familiarity with agentic AI tools is a plus (preferred).
  • Experience in AI/ML workloads.

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