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Product Development Lifecycle Data Analytics User Experience Research Jira Confluence SharePoint Excel PowerPoint Artificial Intelligence Project Management Market Research +6 more Show less

FPGA VHDL Verilog DSP Digital Signal Processing HLS ModelSim Synplicity Xilinx Vivado Altera Quartus MATLAB SystemC C C++ Git Bitbucket JIRA Ethernet PCIe SDRAM DDR3 +16 more Show less

FPGA HDL VHDL C C++ Matlab DSP Electronic Warfare System Integration and Test DOORS MS Project Signal Processing Digital Design Configuration Control +9 more Show less

Digital Design Mixed Signal FPGA Silicon Bring-up Characterization Debug MIPI SoundWire I2S SPMI Audio Amplifier Codec Power Converters Micro-architecture Verification Emulation +11 more Show less

UVM OVM SystemVerilog Assertions (SVA) Verilog VHDL Python TCL Perl Mixed-Signal Verification Logic Synthesis Static Timing Analysis Formal Verification Place and Route EDA Tools CMOS Bipolar Scripting +12 more Show less

Digital Design Mixed Signal FPGA Silicon Bring-up Characterization Debug MIPI SoundWire I2S SPMI Audio Amplifier Codec Power Converters Micro-architecture Emulation Verification Validation +12 more Show less

Digital Design Mixed Signal Design FPGA Silicon Bring-up Characterization Debug MIPI SoundWire I2S SPMI Audio Amplifier Codec Power Converters Micro-architecture Emulation Verification +11 more Show less

ASIC Design RTL Coding Digital Design HBM LPDDR DDR NoC SRAM Cache Controller x86 ARM Gate Level Simulation Synthesis Timing Closure Power Analysis Hardware Architecture +11 more Show less

RTL Design ASIC FPGA Microarchitecture Synthesis Static Timing Analysis Clock Domain Crossing CDC Tape-out FinFET EDA Tools JIRA Power Analysis Bus Fabric Formal Verification Physical Verification Microsoft Office +12 more Show less

ASIC RTL Design Verilog System Verilog VHDL Python Perl SoC Logic Design System Simulation Clock Design +6 more Show less

API SWIFT ISO 20022 JSON Open Banking SAP Oracle ERP Treasury Management Systems Fintech Mobile Platforms Technical Demonstrations Cash Management Payables Receivables Liquidity Foreign Exchange +11 more Show less

ASIC Design RTL Coding HBM LPDDR DDR NoC SRAM Cache Controller x86 ARM Synthesis Timing Closure Gate Level Simulation Power Analysis Digital Design Hardware Architecture +11 more Show less

ASIC Design RTL Coding HBM LPDDR DDR NoC SRAM Cache Controller x86 ARM Synthesis Timing Closure Gate Level Simulation Power Analysis Digital Design Hardware Architecture +11 more Show less

Digital Design FPGA Silicon Bring-up Characterization Debug Mixed Signal Design MIPI HDMI TCON Micro-architecture Emulation Verification +7 more Show less

Digital Design FPGA Silicon Bring-up Characterization Debug Mixed Signal Design MIPI HDMI TCON Micro-architecture Emulation Verification +7 more Show less

Digital Design FPGA Silicon Bring-up Characterization Mixed Signal Design MIPI HDMI TCON Micro-architecture Emulation Verification Validation +7 more Show less

Verilog SystemVerilog ASIC Design RTL Synopsys Synthesis Low Power Design Computer Architecture C C++ Python Design Verification SOC Interconnects Memory Subsystems +8 more Show less

RTL ASIC FPGA Synthesis Static Timing Analysis Clock Domain Crossing CDC Bus Fabric Formal Verification Simulation JIRA FinFET TSMC GlobalFoundries Samsung EDA Tools Microarchitecture Power Analysis +13 more Show less

Verilog System Verilog RTL UVM SerDes Ethernet InfiniBand PCIe USB Silicon Photonics Static Timing Analysis Synthesis Firmware Co-Packaged Optics CDR DFE CTLE +12 more Show less

API SWIFT ISO 20022 JSON Open Banking SAP Oracle ERP TMS Fintech Mobile Platforms Technical Demonstrations +7 more Show less