Senior ASIC Digital Design Engineer

General Dynamics

Confirmed live yesterday High trust

Remote Hybrid

Quick summary

Work type: Remote
Location: Annapolis Junction, MDBoise, IDSalt Lake City, UTBloomington, MN
Salary: $142,166–$150,000 / yr
Posted: 45 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $193k

This role $146k

$133k most similar roles pay here $228k

This role pays less than 92% of similar roles. Most pay $169,500–$216,250 — the shaded band above. At the midpoint, this role pays about $146k versus about $193k for comparable roles.

Based on 240 similar postings.

Employer

About General Dynamics

General Dynamics is a global aerospace and defense company offering a broad portfolio of products and services in business aviation, ship construction, land combat vehicles, and information technology. It serves customers in the U.S. government, allied governments, and a diverse array of commercial markets.

General Dynamics currently has 1123 open roles on FindRole.

Listed pay typically runs $124,093–$150,385 across 984 roles with salary data.

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View all roles at General Dynamics

At a glance

TL;DR · Senior ASIC Digital Design Engineer

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As a Senior ASIC Digital Design Engineer, you will join a high-performing team to take ownership of critical design tasks throughout the full ASIC and FPGA lifecycle. You will develop RTL with a focus on bus fabric integrity, clock domain crossings, and reset order-of-operations while ensuring correctness through rigorous simulation and formal verification. Your daily responsibilities include contributing to timing closure via synthesis and static timing analysis, participating in JIRA triage, performing code reviews, and supporting program planning and technology evaluations. The role requires expertise in RTL design, microarchitecture, CDC analysis, and power analysis basics using industry-standard EDA tools for synthesis and simulation. You will work within structured environments involving formal verification processes to solve complex hardware problems, potentially utilizing FinFET process nodes and commercial foundry flows to ensure reliable silicon results.

Skills

RTL ASIC FPGA Synthesis Static Timing Analysis Clock Domain Crossing CDC Bus Fabric Formal Verification Simulation JIRA FinFET TSMC GlobalFoundries Samsung EDA Tools Microarchitecture Power Analysis

What you'll do

Develop RTL with a focus on bus fabric integrity, clock domain crossings, reset order-of-operations, and design-for-verification.
Resolve timing failures by working through synthesis, place and route, and static timing analysis.
Execute test and simulation plans in coordination with a dedicated verification team to drive functional closure.
Participate in RTL code reviews to provide and receive constructive technical feedback.
Manage the project backlog by triaging issues and maintaining an accurate status in JIRA.
Provide technical input on scope, level of effort, and schedule risks for program planning and proposals.
Evaluate foundry technologies, device libraries, IP cores, and EDA tooling.

What we're looking for

U.S. citizenship is required.
Ability to obtain a Department of Defense Secret security clearance is required.
Bachelor's degree in Electrical or Computer Engineering, or a related STEM field, with 5+ years of experience; or a Master's degree plus 3 years of experience.
5+ years of ASIC/FPGA design experience as an RTL designer.
Experience working in large, structured design teams with formal verification processes and independent verification partners.
Working knowledge of RTL design, microarchitecture, bus fabric, clock domain crossing (CDC), reset sequencing, timing closure, and power analysis.
Familiarity with industry-standard EDA tools for synthesis, simulation, formal verification, and STA.
Experience contributing to ASIC tape-out efforts (preferred); familiarity with FinFET process nodes (7nm, 5nm) (preferred).

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