Digital ASIC Design Engineer

Qualcomm

Confirmed live yesterday Trusted

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $98,500–$147,700 / yr
Posted: 23 days ago
Freshness: Confirmed live yesterday
Closes: Feb 15, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $196k

This role $123k

$83k most similar roles pay here $246k

This role pays less than 97% of similar roles. Most pay $168,425–$223,175 — the shaded band above. At the midpoint, this role pays about $123k versus about $196k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

Most-posted roles

View all roles at Qualcomm

At a glance

TL;DR · Digital ASIC Design Engineer

Role Posting Log in to save

As a Digital ASIC Design Engineer within the ASICS Engineering group, you will join a fast-paced SoC team focused on high performance ASICs in sub-4nm processes for mobile, automotive, compute, AI, and XR applications. You will be responsible for the definition, modeling, design, optimization, verification, validation, and documentation of IP blocks and SoCs. Your daily work involves executing architecture and logic designs, performing system simulations, and resolving complex design or verification problems using established engineering practices. You will specifically focus on clock and power-related features while identifying improvements for flow and process methodologies. The role requires proficiency in RTL design using Verilog, System Verilog, or VHDL, along with experience in automation and scripting languages such as Python or Perl to support the development of next-generation hardware components.

Skills

ASIC RTL Design Verilog System Verilog VHDL Python Perl SoC Logic Design System Simulation Clock Design

What you'll do

Define, model, design, and optimize IP blocks and SoCs for high-performance products.
Execute the architecture and design of SoCs according to established design protocols.
Resolve complex architecture, design, and verification problems using standard ASIC engineering practices.
Support verification efforts for ASICs, SoC, and specific IP cores with a focus on clock and power features.
Perform analysis and design of various integrated circuits (IPs).
Identify and implement improvements for internal flows and processes.
Incorporate silicon learnings to improve design methodology and IP development.

What we're looking for

Bachelor's degree in Science, Engineering, or a related field.
Experience in RTL design using Verilog, System Verilog, or VHDL.
Proficiency in automation or scripting languages such as Python or Perl.
Master's degree in Electrical Engineering, Computer Science, or Computer Engineering (preferred).
6+ months of relevant experience in ASIC design, scripting, and architecture (preferred).
Specific experience in clock design of ASIC/SoC (preferred).

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