High-Speed HBM, LPDDR Memory Subsystem ASIC Digital Design Engineer

Qualcomm

Confirmed live yesterday Trusted

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $140,000–$210,000 / yr
Posted: 30 days ago
Freshness: Confirmed live yesterday
Closes: Feb 8, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $200k

This role $175k

$129k most similar roles pay here $241k

This role pays less than 73% of similar roles. Most pay $175,000–$224,175 — the shaded band above. At the midpoint, this role pays about $175k versus about $200k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · High-Speed HBM, LPDDR Memory Subsystem ASIC Digital Design Engineer

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Next-Gen, High-Speed HBM, LPDDR Memory Subsystem ASIC Digital Design Engineer joins the Memory and Cache Controller and Advanced Memory NoCs based Subsystem Design Team to develop high-speed memory subsystems for QCT products. This role involves developing architecture and design specifications, driving micro-architecture for logic designs, and performing RTL coding to enable 1GHz+ designs. The engineer will be responsible for debugging designs, providing integration support, and executing synthesis, timing closure, physical design support, gate level simulations, and power analysis. Key technical requirements include experience with LPDDR memory, cache controllers, NoC based architectures, HBM memory types, and on-chip SRAM and L3 cache controller architecture. The role requires expertise in x86 or ARM CPU/bus architectures and the ability to manage memory transaction ordering to conform to ISA architecture specifications within high-speed digital design environments.

Skills

ASIC Design RTL Coding HBM LPDDR DDR NoC SRAM Cache Controller x86 ARM Synthesis Timing Closure Gate Level Simulation Power Analysis Digital Design Hardware Architecture

What you'll do

Develop architecture and design specifications for high-speed HBM, LPDDR, and DDR memory subsystems.
Write RTL code to implement high-speed (1GHz+) designs for QCT products.
Drive the micro-architecture of specific logic design components.
Collaborate with verification engineers to deliver high-quality designs.
Debug your own designs and provide support when integrated into the larger chip.
Perform synthesis, timing closure, physical design support, gate level simulations, and power analysis.
Contribute to improvements in design methodology to increase productivity and quality of results.

What we're looking for

Bachelor's degree in Science, Engineering, or a related field.
Master's degree in Computer Engineering or Electrical Engineering is preferred.
5+ years of experience in ASIC design, RTL coding, and front-end digital design.
3+ years of Hardware Architecture experience.
Experience with high-speed digital design (1GHz+) for memory subsystems like HBM, LPDDR, and DDR.
Experience with NoC based architectures and cache controller designs.
Familiarity with x86 or ARM CPU/bus architectures and ISA architecture specifications.
Knowledge of RTL Design Verification flows is preferred.