Lead ASIC Digital Design Engineer

General Dynamics

Confirmed live yesterday High trust

Hybrid

Quick summary

Work type: Hybrid
Location: Sudbury, MABoiseSalt Lake City, UTBloomington, MNAnnapolis Junction, ME
Salary: $176,512–$187,000 / yr
Posted: 9 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $201k

This role $182k

$141k most similar roles pay here $240k

This role pays less than 58% of similar roles. Most pay $175,000–$226,350 — the shaded band above. At the midpoint, this role pays about $182k versus about $201k for comparable roles.

Based on 240 similar postings.

Employer

About General Dynamics

General Dynamics is a global aerospace and defense company offering a broad portfolio of products and services in business aviation, ship construction, land combat vehicles, and information technology. It serves customers in the U.S. government, allied governments, and a diverse array of commercial markets.

General Dynamics currently has 1123 open roles on FindRole.

Listed pay typically runs $124,093–$150,385 across 984 roles with salary data.

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At a glance

TL;DR · Lead ASIC Digital Design Engineer

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The Lead ASIC Digital Design Engineer joins a high-performing team to take ownership of the full ASIC and FPGA design lifecycle. This technical role focuses on RTL design, where the engineer will develop bus fabric integrity, manage clock domain crossings, and oversee reset order-of-operations. Day-to-day responsibilities include driving timing closure through synthesis and static timing analysis, leading verification efforts with test plans, conducting code reviews, and managing JIRA backlogs. The candidate must evaluate foundry technologies, device libraries, and IP cores while providing technical input for program planning and proposals. Required skills include RTL coding, microarchitecture, power optimization, and experience with FinFET process nodes and commercial foundry flows. The role addresses complex digital hardware development challenges, requiring an engineer who can navigate the intricacies of advanced node design and ensure robust hardware functionality.

Skills

RTL Design ASIC FPGA Microarchitecture Synthesis Static Timing Analysis Clock Domain Crossing CDC Tape-out FinFET EDA Tools JIRA Power Analysis Bus Fabric Formal Verification Physical Verification Microsoft Office

What you'll do

Develop and lead RTL design focusing on bus fabric integrity, clock domain crossings, and reset operations.
Drive timing closure through synthesis, place and route, and static timing analysis to resolve failures.
Develop and execute test and simulation plans to verify results and drive closure on failures.
Manage the JIRA triage process by prioritizing issues and maintaining an actionable backlog.
Conduct RTL code reviews to set technical standards and provide actionable feedback to the team.
Provide technical input for proposal basis of estimates regarding scope, complexity, and effort.
Evaluate foundry technologies, device libraries, IP cores, and EDA tooling to inform design decisions.
Provide data for program planning including Integrated Master Schedule development and Earned Value reporting.

What we're looking for

U.S. citizenship is required for this position.
Ability to obtain a Department of Defense Secret security clearance is required.
A Bachelor's degree in Electrical or Computer Engineering, or a related field, plus 8 years of experience is required.
A Master's degree plus 6 years of relevant experience is an acceptable educational alternative.
Candidates must have ASIC/FPGA design experience with significant time spent as an RTL designer.
Experience contributing to ASIC tape-out efforts, including timing closure and physical verification, is required.
Proficiency in RTL design, microarchitecture, bus fabric, clock domain crossing (CDC), and power optimization is required.
Familiarity with FinFET process nodes and commercial foundry flows is a preferred differentiator.

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