Senior Digital Design Engineer - High-Speed I/O and Photonics

Nvidia

Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CA
Salary: $136,000–$218,500 / yr
Posted: 7 days ago
Nearby: 99+ roles within 25 mi

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Competitive pay

How this pay compares to similar roles

Similar $193k

This role $177k

$125k most similar roles pay here $236k

This role pays less than 55% of similar roles. Most pay $170,000–$216,250 — the shaded band above. At the midpoint, this role pays about $177k versus about $193k for comparable roles.

Based on 240 similar postings.

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About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 994 open roles on FindRole.

Listed pay typically runs $168,000–$270,250 across 977 roles with salary data.

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At a glance

TL;DR · Senior Digital Design Engineer - High-Speed I/O and Photonics

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As a senior digital design engineer in the mixed-signal high-speed I/O group at NVIDIA, you will play a pivotal role in developing innovative PHY designs for AI systems. Your day-to-day responsibilities include working on advanced DSPs, silicon photonics IPs, and chips, collaborating with analog designers to define micro-architecture specifications and develop calibration algorithms. You will also handle backend design tasks like defining synthesis constraints and driving timing closure while evaluating PPA trade-offs based on feedback from synthesis and place-and-route processes. Post-silicon activities involve participating in bring-up, testing, debugging, characterization, performance tuning, and production support. The ideal candidate has a B.S. or M.S. degree in Electrical Engineering with 5+ years of experience in high-speed digital design, proficiency in Verilog/System Verilog, and knowledge of optical transceiver devices, SerDes architecture, and mixed-signal circuit concepts.

Skills

Verilog SystemVerilog UVM SerDes CDR DFE CTLE TXFIR Python Perl Tcl VHDL ModelSim Cadence Synopsys Calibre Linux Git CI/CD

What you'll do

Develop micro-architecture specifications for high-speed DSPs and silicon photonics IPs.
Create calibration and adaptation algorithms for digital assist analog designs.
Define synthesis constraints and drive timing closure in backend design processes.
Evaluate PPA trade-offs based on synthesis and physical implementation feedback.
Participate in post-silicon bring-up, testing scripts creation, and performance tuning.

What we're looking for

5+ years of experience in high-speed digital design with proficiency in front-end design flow and tools.
Deep understanding of Verilog or System Verilog, logic design concepts, and typical structures.
Experience with optical transceiver devices and integrated components like modulators, detectors, TIAs.
Knowledge of SerDes architecture including CDR, DFE, CTLE, TXFIR building blocks.
Familiarity with mixed-signal circuit design concepts and behavior modeling of mixed-signal circuits.
Understanding of physical layer communication protocols such as Ethernet, InfiniBand, PCIe, USB.

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