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UVM OVM SystemVerilog Assertions (SVA) Verilog VHDL Python TCL Perl Mixed-Signal Verification Logic Synthesis Static Timing Analysis Formal Verification Place and Route EDA Tools CMOS Bipolar Scripting +12 more Show less

Digital Design Mixed Signal FPGA Silicon Bring-up Characterization Debug MIPI SoundWire I2S SPMI Audio Amplifier Codec Power Converters Micro-architecture Emulation Verification Validation +12 more Show less

Digital Design Mixed Signal Design FPGA Silicon Bring-up Characterization Debug MIPI SoundWire I2S SPMI Audio Amplifier Codec Power Converters Micro-architecture Emulation Verification +11 more Show less

ASIC Design RTL Coding Digital Design HBM LPDDR DDR NoC SRAM Cache Controller x86 ARM Gate Level Simulation Synthesis Timing Closure Power Analysis Hardware Architecture +11 more Show less

RTL Design ASIC FPGA Microarchitecture Synthesis Static Timing Analysis Clock Domain Crossing CDC Tape-out FinFET EDA Tools JIRA Power Analysis Bus Fabric Formal Verification Physical Verification Microsoft Office +12 more Show less

FPGA RTL VHDL Verilog SystemVerilog SoC Python Tcl Linux Git CI/CD Xilinx Ethernet PCIe JESD204 SPI I2C UART CAN MIL-STD-1553 +15 more Show less

Instructional Design Storyboarding e-Learning Web 2.0 Blended Learning ILT Security+ CCNA Security CySA+ GICSP GSEC SSCP Cloud Hybrid Cloud AI +10 more Show less

Figma Google Suite Design Systems UX Strategy Digital Design Copywriting +1 more Show less

Verilog SystemVerilog FPGA UVM AXI4 AXI‑Stream JESD204(B Aurora Ethernet PCIe Vivado Vitis Quartus Tcl Python C++ HLS Git Azure DevOps CI/CD Linux Windows +17 more Show less

FPGA RTL VHDL Verilog SystemVerilog SoC Python Tcl Linux Git CI/CD Xilinx Vitis Ethernet PCIe JESD204 SPI I2C UART CAN MIL-STD-1553 +16 more Show less

ASIC RTL Design Verilog System Verilog VHDL Python Perl SoC Logic Design System Simulation Clock Design +6 more Show less

API SWIFT ISO 20022 JSON Open Banking SAP Oracle ERP Treasury Management Systems Fintech Mobile Platforms Technical Demonstrations Cash Management Payables Receivables Liquidity Foreign Exchange +11 more Show less

Figma Adobe XD Adobe Experience Manager (AEM) Adobe Target Optimizely HTML CSS WCAG Storyports Litmus UX Design Mockups Email Marketing Analytics +9 more Show less

ASIC Design RTL Coding HBM LPDDR DDR NoC SRAM Cache Controller x86 ARM Synthesis Timing Closure Gate Level Simulation Power Analysis Digital Design Hardware Architecture +11 more Show less

FPGA Circuit Design OrCAD Xpedition PCB Layout SoC System Simulation Synthesis Place and Route Power Utilization AI +6 more Show less

VLSI RTL Design micro architecture Synthesis Silicon Engineering Power Control Systems ASIC +2 more Show less

High-speed Digital Design Baseband Design Signal Integrity Analysis Simulation Power Management ICs RF Debug PWB Layout BOM Capture Firmware Development Integration +5 more Show less

ASIC Design RTL Coding HBM LPDDR DDR NoC SRAM Cache Controller x86 ARM Synthesis Timing Closure Gate Level Simulation Power Analysis Digital Design Hardware Architecture +11 more Show less

Verilog RTL Design ASIC Ethernet TCP/IP MPLS Python Perl Timing Closure Clock Domain Crossing Low Power Design Packet Processing Digital Design Micro-architecture ECO Implementation +10 more Show less

Digital Design FPGA Silicon Bring-up Characterization Debug Mixed Signal Design MIPI HDMI TCON Micro-architecture Emulation Verification +7 more Show less