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ASIC SoC RTL GDS2 FPGA SerDes DSP SPI I2C APB AXI Ethernet DFT Synthesis Timing Closure Low-Power Design Scripting +12 more Show less

Verilog SystemVerilog VHDL Python Perl SPICE HSPICE CMOS FinFET Cadence Synopsys EDA Tools Digital Circuit Design SRAM Timing and Delay Analysis Power Management Monte Carlo SerDes Object-Oriented Programming Operating Systems +15 more Show less

Digital Hardware Design Schematic Capture PCB Layout FPGA Embedded Processors PCIe DDR3 DDR4 SDRAM JESD UART SPI 1000BASE-T Mentor Graphic’s Git ClearCase Confluence Logic Analyzers BERTs Signal Intelligence Machine Learning Image Processing +17 more Show less

Product Development Life Cycle Data Analytics Payments Domain AI Product Roadmap Requirements Definition Product Backlog Market Research Digital Payment Portals Rules-based Recommendation Systems Product Measurement Frameworks Cross-functional Delivery +7 more Show less

Change Management root-cause analysis AI Data Analytics Product Development Life Cycle Business Continuity Automation Product Roadmap Requirements Definition Dashboards Metrics +6 more Show less

FPGA VHDL Digital Signal Processing DSP Vivado Quartus Libero MATLAB Simulink Xilinx Altera Microsemi RF Digital Circuit Design Schematic Generation PWB Layout Oscilloscope Logic Analyzer Signal Generator +14 more Show less

FPGA VHDL Digital Signal Processing Vivado Quartus Libero MATLAB Simulink AMD (Xilinx Intel (Altera Microchip (Microsemi Circuit Design Schematic Generation PWB Layout Oscilloscope Logic Analyzer Signal Generator RF Encryption +14 more Show less

HSIO UCIe BOW PCIe AXI CHI CXS.B CXL UA-Link DFT Ethernet PMA Signal Integrity Power Integrity Digital Design Flow Mixed-Signal Design +10 more Show less

ASIC Design RTL Design SystemVerilog Verilog Computer Architecture Synopsys Synthesis Low Power Design Python C++ C Coverage-based Design Verification SoC Interconnects Memory Controllers micro architecture Debugging +10 more Show less

Payments API ISO 20022 H2H Product Development Life Cycle Data Analytics Enterprise Architecture File-based Connectivity Integration Patterns Platform Design Transaction Reporting CAMT Product Roadmap +8 more Show less

SRAM Design RTL Cadence Virtuoso SPICE Model Sim Digital P&R Static Timing Analysis PrimeTime NanoTime Skill DFT GDS WaveView SpiceExplorer Layout Tools +10 more Show less

RTL SRAM Design Cadence Virtuoso SPICE Static Timing Analysis PrimeTime DFT IR/EM Machine Learning Circuit Design Schematic Capture Power Gating Clock Gating Spice Explorer +9 more Show less

Digital Hardware Design Schematic Capture FPGA Micro Processors Micro Controllers Signal Integrity Digital Signal Processing Worst Case Analysis Stress Analysis High Reliability Controlled Impedance +6 more Show less

RTL Design Digital Implementation ASIC Physical Design DFT TCL Python SKILL Perl Cadence Innovus Siemens Calibre Siemens QuestaSim Tessent Virtuoso LEC CDC Lint +12 more Show less

ASIC SoC RTL GDS2 FPGA SerDes Ethernet SPI I2C APB AXI DFT Synthesis Timing Closure DSP Scripting +11 more Show less

AI Causal Inference Real-World Evidence Data Science SQL Knowledge Graphs Foundation Models Agentic AI Agile Lean Methodologies Jira Confluence Miro Lucidchart UX/UI System Integration Data Analytics +12 more Show less

User Centered Design Design Thinking API Data Analysis Process Engineering KPIs KRIs UX Strategy Analytics Research Testing +7 more Show less

ASIC RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Design Verification Scripting Logic Design +4 more Show less

Analog Design VLSI Design Hspice Verilog Static Timing Analysis PnR SRAM Compiler Design Schematic Capture Power Efficiency silicon bring up Physical Design +6 more Show less

C C++ Python Verilog SystemVerilog Perl Matlab Vulkan UVM RTL ASIC SoC DSP LTE 5G Wi-Fi Linux Windows Machine Learning +14 more Show less