Staff HSIO Digital & Mixed Signal Design Engineer

Samsung Semiconductor

Confirmed live today High trust

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$163,000–$253,000 / yr
Posted
14 days ago
Freshness
Confirmed live today

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Competitive pay

How this pay compares to similar roles

Similar $205k
This role $208k
$147k $264k
below market most similar roles pay here above market

This role pays more than 52% of similar roles. Most pay $177,250–$233,137 — the blue band above. At the midpoint, this role pays about $208k versus about $205k for comparable roles.

Based on 240 similar postings.

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About Samsung Semiconductor

Samsung Semiconductor is the global semiconductor business unit of Samsung Electronics, designing and manufacturing memory chips, logic semiconductors, and foundry solutions for a broad range of applications.

Samsung Semiconductor currently has 36 open roles on FindRole.

Listed pay typically runs $163,000–$253,000 across 36 roles with salary data.

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At a glance

TL;DR · Staff HSIO Digital & Mixed Signal Design Engineer

The Staff HSIO Digital & Mixed Signal Design Engineer joins the Location Group to develop next-generation High-Speed I/O for AI production platforms. This role involves working on the end-to-end digital design flow for die-to-die chiplet interfaces, requiring collaboration with system and analog teams. Key responsibilities include handling HSIO PHY IP, such as UCIe, BOW, and PCIe, while managing design trade-offs for high-speed serial interconnect protocols. The engineer must apply knowledge of Signal Integrity and Power Integrity modeling, as well as Design for Testability methodologies. Technical requirements include proficiency with SoC protocols like AXI, CHI, CXS.B, CXL, and UA-Link, along with familiarity with Ethernet PMA, PMD, and PCS layers. The work focuses on building integrated products for mobile and wearable applications within the broader SoC organization.

What you'll do

  • Design next-generation High-Speed I/O (HSIO) for AI production platforms.
  • Develop digital design for die-to-die chiplet interfaces and similar high-speed technologies.
  • Manage the end-to-end digital design flow from concept to productization.
  • Implement high-speed serial interconnect protocols and evaluate associated design trade-offs.
  • Model Signal Integrity (SI) and Power Integrity (PI) for High-Speed I/O designs.
  • Integrate analog and mixed-signal design and verification into digital-on-top development flows.
  • Apply Design for Testability (DFT) methodologies and flows to the design process.
  • Optimize solutions for SoC products including Application Processor and Communication Processor lines.

What we're looking for

  • Must have a BS in Electrical Engineering with 10+ years of experience, an MS with 8+ years, or a PhD with 5+ years.
  • Must have 3+ years of industry experience specializing in digital design for die-to-die (chiplet) interfaces or similar high-speed I/O technologies.
  • Must have hands-on experience with HSIO PHY IP, such as UCIe, BOW, or PCIe.
  • Must have a deep understanding of high-speed serial interconnect protocols and associated design trade-offs.
  • Must have a strong understanding of how analog and mixed-signal design and verification impact digital-on-top development flows.
  • Must have knowledge of Signal Integrity (SI) and Power Integrity (PI) modeling for High-Speed I/O designs.
  • Must understand SoC protocols including AXI/CHI/CXS.B/CXL/PCIE/UA-Link.
  • Must have knowledge of Design for Testability (DFT) methodologies and flows.
  • Must have familiarity with Ethernet PMA / PMD / PCS layers.

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