Digital IC Design Manager

What you'll do

• Manage a team of digital and physical design engineers to create RTL code and physical implementations.
• Execute and continuously improve RTL design and RTL-to-gds digital implementation flows for display ICs.
• Perform logic design, Design-for-Test, chip floorplanning, place-and-route, timing closure, and physical verification.
• Oversee synthesis, DFT insertion, and Logic Equivalence Checking (LEC) for ASIC projects.
• Specify and configure design tools and develop automation scripts using TCL, Python, or Perl.
• Hire and manage new staff while overseeing performance management and HR procedures.
• Work with chip architects and analog design teams to develop Big-D and Big-A type ASICs.

What we're looking for

• Hold a BSEE or MSEE degree.
• Have 10+ years of experience in physical design or digital implementation.
• Have a minimum of 3 years of experience in a management role.
• Possess strong knowledge of logic design, RTL coding, and associated functions like lint, CDC, LEC, and DFT.
• Possess strong knowledge of digital implementation, including physical design, synthesis, and timing closure.
• Possess strong knowledge of Cadence Innovus, Tempus, Genus, PVS, and Mentor/Siemens Calibre tool suites.
• Demonstrate proficiency in scripting and automation using TCL, SKILL, Perl, Python, and Shell scripts.
• Knowledge of Analog/Mixed-signal design, Siemens QuestaSim, Veloce Emulator, Tessent DFT, and Virtuoso (preferred).