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Director, Cache RTL

Amd

Fort Collins, CO 3 days ago $216,080–$324,120
Actively hiring Confirmed live today Posted this week High trust Above market
RTL Design Microarchitecture Verilog SystemVerilog HDL Cache Architecture CPU Coherency SoC Chiplet Lint CDC RDC Scripting Low-Power Design RAS ECC Tapeout Physical Design Design For Test
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CPU Cache Architect

Amd

Remote (Fort Collins, CO) 6 days ago $200,000–$300,000
Actively hiring Confirmed live yesterday Posted this week High trust Above market
C++ Verilog HDL Digital RTL Design Computer Architecture SoC Performance Modeling Performance Analysis Simulators Emulation Post-silicon Observation Scripting Hardware Design Microarchitecture
Remote
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CPU Cache Architect

Amd

Remote (Fort Collins, CO) 6 days ago $144,800–$217,200
Actively hiring Confirmed live today Posted this week High trust Below market
C++ Verilog HDL Digital RTL Design Computer Architecture SoC Performance Modeling Performance Analysis Emulation Post-silicon Observation Scripting Hardware Design Microarchitecture
Remote
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Next-Gen System Cache ASIC Digital Design Engineer

Qualcomm

San Diego, CA 20 days ago $121,800–$182,600
Actively hiring Confirmed live today High trust Below market
ASIC Design RTL Design SystemVerilog Verilog Computer Architecture Synopsys Synthesis Low Power Design Python C++ C Coverage-based Design Verification SoC Interconnects Memory Controllers micro architecture Debugging
2+ yrs exp
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Next Gen High-Speed Memory and Cache Controller Design Engineer

Qualcomm

San Diego, CA 20 days ago $101,400–$152,200
Actively hiring Confirmed live today Trusted Below market
ASIC Design RTL LPDDR HBM DDR NoC SRAM Cache Controller x86 ARM Synthesis Timing Closure Gate Level Simulation Power Analysis Physical Design Micro-architecture ISA
3+ yrs exp
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CPU Microarchitecture & Cache RTL Design Engineer

Amd

Fort Collins, CO 34 days ago $144,800–$217,200
Actively hiring Confirmed live today High trust Below market
VLSI RTL Design Verilog HDL Cache Architecture CPU Coherency NoC SoC Scripting Microarchitecture Timing Closure Design for Test Physical Design Routing Fabric
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CPU Cache Microarchitect/RTL Engineer

Apple Inc

Waltham, MA 40 days ago $165,800–$292,400
Actively hiring Confirmed live today Trusted Competitive pay
RTL Verilog VHDL Microarchitecture CPU Cache C C++ Python Perl Formal Methods Simulation Emulation DFT SRAM Coherence Protocols Interconnects
10+ yrs exp
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CPU Cache Microarchitect/RTL Engineer

Apple Inc

Santa Clara, CA 40 days ago $184,700–$324,800
Actively hiring Confirmed live yesterday Trusted Above market
RTL Design Verilog VHDL Microarchitecture C C++ Python Perl Formal Methods Simulation Emulation DFT SRAM Design Coherence Protocols Interconnects Power Management
10+ yrs exp
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CPU Cache Microarchitect/RTL Engineer

Apple Inc

Beaverton, OR 40 days ago
Actively hiring Confirmed live today Low trust
RTL Verilog VHDL Microarchitecture C C++ Python Perl Formal Methods Simulation Emulation DFT SRAM Coherence Protocols Interconnects Power Management
10+ yrs exp
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CPU Cache Microarchitect/RTL Engineer

Apple Inc

Santa Clara, CA 40 days ago $150,400–$277,600
Actively hiring Confirmed live today Trusted Competitive pay
RTL Design Verilog VHDL Microarchitecture C C++ Python Perl Formal Methods Simulation Emulation DFT SRAM Design Coherence Protocols Interconnects Power Management
3+ yrs exp
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Graphics Cache Hierarchy Design Verification Engineer

Apple Inc

Santa Clara, CA 40 days ago $150,400–$277,600
Actively hiring Confirmed live today Trusted Competitive pay
SystemVerilog UVM Verilog VHDL RTL Verification Computer Architecture GPU Architecture Cache Verification Memory Management Unit Shell Scripting Perl Ruby Makefiles HDL Simulators Waveform Viewers Functional Coverage SoC
3+ yrs exp
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Graphics Cache Hierarchy Design Verification Engineer

Apple Inc

Santa Clara, CA 40 days ago $129,300–$194,700
Actively hiring Confirmed live yesterday Trusted Below market
SystemVerilog Verilog RTL Verification Computer Architecture GPU Architecture Object Oriented Programming Data Structures Perl Ruby Shell Scripting Makefiles HDL Simulators Waveform Viewers Caches Memory Management Unit Interconnects
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CPU Cache Microarchitect/RTL Engineer

Apple Inc

Santa Clara, CA 40 days ago $150,400–$277,600
Actively hiring Confirmed live today Trusted Competitive pay
RTL Verilog VHDL Microarchitecture C C++ Python Perl Simulators Formal Methods DFT SRAM Coherence Protocols Interconnects Power Management
3+ yrs exp
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CPU Cache Microarchitect/RTL Engineer

Apple Inc

Waltham, MA 40 days ago $165,800–$292,400
Actively hiring Confirmed live today Trusted Competitive pay
RTL Verilog VHDL Microarchitecture C C++ Python Perl Formal Methods Simulation Emulation DFT SRAM Coherence Protocols Interconnects Power Management
10+ yrs exp
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CPU Cache Microarchitect/RTL Engineer

Apple Inc

Santa Clara, CA 40 days ago $184,700–$324,800
Actively hiring Confirmed live yesterday Trusted Above market
RTL Verilog VHDL Microarchitecture CPU Cache C C++ Python Perl Formal Methods Simulation Emulation DFT SRAM Coherence Protocols Interconnects
10+ yrs exp
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CPU Cache Microarchitect/RTL Engineer

Apple Inc

Beaverton, OR 40 days ago
Actively hiring Confirmed live today Low trust
RTL Verilog VHDL Microarchitecture C C++ Python Perl Formal Methods Simulation Emulation DFT SRAM Coherence Protocols Interconnects Power Management
10+ yrs exp
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Senior Software Developer, RPMS/FileMan/M/Cache

General Dynamics

Remote (Silver Spring, MD) 60 days ago $129,813–$146,050
Actively hiring Confirmed live today High trust Below market
FileMan M-Code Cache RPMS Azure DevOps Team Foundation Server Agile QA Lifecycle System Design VISTA CPRS IHS VA
8+ yrs exp Remote
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Senior ASIC Physical Design Engineer, Cache Coherent Interconnects

Nvidia

Santa Clara, CA +1 78 days ago $136,000–$218,500
Actively hiring Confirmed live yesterday High trust Competitive pay
Physical Design ASIC Design Flow Synthesis Timing Analysis Verilog RTL Design DFT ECO Floor-planning High-Frequency Design Micro-architecture
5+ yrs exp
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ASIC Design Engineer, Cache Controller

Apple Inc

Santa Clara, CA 89 days ago $129,300–$194,700
Actively hiring Confirmed live today High trust Below market
RTL Micro-architecture SoC Cache Coherence Protocols DRAM Controller Timing Closure Memory Subsystems Interconnect Architectures
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Graphics Cache Hierarchy Design Verification Engineer

Apple Inc

Santa Clara, CA 91 days ago $150,400–$277,600
Actively hiring Confirmed live yesterday Low trust Competitive pay
SystemVerilog UVM Verilog VHDL RTL Verification Computer Architecture GPU Architecture Cache Verification Memory Management Unit Shell Scripting Perl Ruby Makefiles HDL Simulators Waveform Viewers Functional Coverage
2+ yrs exp
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