ASIC Design Engineer, Cache Controller

Apple Inc

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Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$129,300–$194,700 / yr
Posted
89 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $198k
This role $162k
$117k $248k
below market most similar roles pay here above market

This role pays less than 78% of similar roles. Most pay $168,200–$227,350 — the blue band above. At the midpoint, this role pays about $162k versus about $198k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · ASIC Design Engineer, Cache Controller

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The ASIC Design Engineer - Cache Controller will join the hardware team to design and develop hardware for the cache subsystem in a high-performance system on a chip. The role involves developing cache micro-architecture based on architecture guidelines and model analysis while exploring trade-offs in system performance, area, and power consumption. Key responsibilities include developing and debugging register-transfer level design for various sections of the cache subsystem, performing front-end netlist and area/timing analysis, and collaborating with the physical design team on timing closure. Candidates must possess in-depth knowledge of memory subsystems, RTL development, and PPA trade-offs. The work focuses on solving design challenges for high-bandwidth multi-client memory subsystems that require real-time, low-latency, and high-bandwidth capabilities within the SOC memory hierarchy.

What does a ASIC Design Engineer earn in California?

Median $214000 from 49 postings across 7 companies.

See salary data

Skills

RTL Micro-architecture SoC Cache Coherence Protocols DRAM Controller Timing Closure Memory Subsystems Interconnect Architectures

What you'll do

  • Design and develop hardware for the cache subsystem in high-performance SoCs.
  • Develop cache micro-architecture based on architecture guidelines and model analysis.
  • Explore architecture trade-offs regarding system performance, area, and power consumption.
  • Develop and debug register-transfer level (RTL) designs for various cache subsystem sections.
  • Perform front-end netlist and area/timing analysis of the cache subsystem.
  • Work with the physical design team to achieve timing closure for the cache subsystem.

What we're looking for

  • B.S. in a relevant field.
  • M.S. in a relevant field (preferred).
  • In-depth knowledge of memory subsystems.
  • Academic experience with RTL/micro-architecture development.
  • Good understanding of PPA (performance/power/area) tradeoffs.
  • Cache design background including understanding of different memory organizations and tradeoffs (preferred).
  • Experience with multi-processor cache coherence protocols (preferred).
  • Knowledge of high-performance coherent memory systems, interconnect architectures, or DRAM controllers (preferred).

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