Graphics Cache Hierarchy Design Verification Engineer

Apple Inc

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Work type
On-site
Location
Santa Clara, CA
Salary
$150,400–$277,600 / yr
Posted
66 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

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Competitive pay

How this pay compares to similar roles

Similar $210k
This role $214k
$135k most similar roles pay here $293k

This role pays more than 62% of similar roles. Most pay $177,287–$241,750 — the shaded band above. At the midpoint, this role pays about $214k versus about $210k for comparable roles.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3513 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2730 roles with salary data.

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At a glance

TL;DR · Graphics Cache Hierarchy Design Verification Engineer

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As a Graphics Cache Hierarchy Design Verification Engineer within the Silicon Technologies group, you will perform pre-silicon RTL verification of graphics memory subsystem units including Caches, Memory Management Unit, Interconnects, and Link interface units. You will collaborate with design leads and architects to develop verification plans, build and maintain portable test bench components, and generate directed and constrained random tests. Your daily work involves running simulations, debugging design issues, creating functional coverage points, and developing automated verification flows for block verification. To succeed in this role, you must possess a strong computer architecture background and proficiency in SystemVerilog, VHDL, Verilog, and UVM. You will also utilize HDL simulators, waveform viewers, and scripting languages like Perl, Ruby, or Shell to verify complex GPU designs and ensure seamless integration within the broader system-on-chip architecture.

Skills

SystemVerilog UVM RTL Verification Verilog VHDL Perl Ruby Shell Scripting Makefiles SoC GPU Architecture Memory Management Unit Cache Hierarchy Functional Coverage Simulation Waveform Viewers

What you'll do

  • Perform pre-silicon RTL verification of graphics memory subsystem units including caches, MMUs, and interconnects.
  • Develop comprehensive verification plans in coordination with design leads and architects.
  • Build and maintain portable verification test bench components and environments.
  • Generate directed and constrained random tests to validate complex designs.
  • Run simulations and debug hardware and environment issues using HDL simulators and waveform viewers.
  • Create functional coverage points and analyze results to identify and close coverage holes.
  • Develop automated verification flows for block-level verification tasks.

What we're looking for

  • Bachelor of Science degree and minimum of 2 years of experience.
  • Experience in CPU or GPU architecture.
  • Experience developing unit or cluster level test environments.
  • Experience driving bring up and debug of complex designs.
  • Experience with verification languages such as SystemVerilog.
  • Experience with HDL simulators and waveform viewers.
  • Experience with cache verification and memory subsystem testing (preferred).
  • Experience with common verification methodologies such as UVM (preferred).

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