CPU Cache Microarchitect RTL Engineer

The CPU Cache Microarchitect/RTL Engineer joins the Silicon Engineering Group to drive multi-level cache subsystem architecture and RTL development for multi-processor systems. This role involves micro-architecture development from high-level exploration through detailed specification, alongside owning RTL design to meet specific power, performance, area, and timing goals. The engineer will perform performance exploration, support verification teams with test bench development and formal methods, and collaborate on physical design implementation. Key technical requirements include expertise in microprocessor architecture, logic design principles, Verilog or VHDL, and experience with simulators and waveform debugging. Preferred skills include knowledge of coherence protocols, interconnects, memory subsystem queuing, SRAM design, and power management strategies. The role focuses on the technical challenge of designing high-performance, low-power microprocessors for complex multi-processor systems while ensuring reliability and testability across various hardware components.