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Active Keyword: CPU Management Remove filter Clear all

20 of up to 20 (filtered)

Director, Product Management, Networking CPU Platforms

Qualcomm

San Diego, CA 41 days ago $198,200–$297,400
Actively hiring Confirmed live yesterday Trusted Competitive pay
CPU Platforms Networking Infrastructure SD‑WAN Silicon Design Platform Software PPA go‑to‑market strategy TAM/SAM Reference Designs Security/Boot Lifecycle Planning SKU Strategy
8+ yrs exp
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Next Gen CPU Power Management RTL Design Engineer

Amd

Santa Clara, CA 47 days ago $166,400–$249,600
Actively hiring Confirmed live yesterday High trust Competitive pay
Verilog SystemVerilog C++ C RTL Design Microarchitecture Power Management Clock Domain Crossing CDC Analysis Firmware DVFS Silicon Validation Design-for-Debug Design-for-Test Digital Design
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CPU Debug and Power Management Verification Engineer

Apple Inc

Beaverton, OR 48 days ago
Actively hiring Confirmed live yesterday Low trust
SystemVerilog UVM SVA Python Perl C++ Assembly AXI UPF FPGA Emulation Formal Verification Post-Silicon Debug Power Management Clock Control RTL Simulation
3+ yrs exp
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CPU Debug and Power Management Verification Engineer

Apple Inc

Beaverton, OR 48 days ago
Actively hiring Confirmed live yesterday Low trust
SystemVerilog UVM SVA Python C++ Assembly Perl AXI FPGA Emulation Formal Verification UPF Low Power Simulation Post-Silicon Debug
10+ yrs exp
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CPU Processor Power Management Verification Engineer

Apple Inc

Santa Clara, CA 48 days ago $184,700–$324,800
Actively hiring Confirmed live yesterday Trusted Above market
System Verilog Verilog UVM Python Perl Assembly Formal Verification UPF FPGA Emulation RTL Digital Logic Power Management Clock Control
10+ yrs exp
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CPU Processor Power Management Verification Engineer

Apple Inc

Santa Clara, CA 48 days ago $150,400–$277,600
Actively hiring Confirmed live 2 days ago Trusted Above market
System Verilog Verilog UVM Python Perl Assembly Formal Verification UPF FPGA Emulation RTL Digital Logic Power Management Clock Control Simulation Testbenches Transactors Assertions
3+ yrs exp
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CPU Processor Power Management Verification Engineer

Apple Inc

Santa Clara, CA 48 days ago $129,300–$194,700
Actively hiring Confirmed live yesterday Low trust Below market
System Verilog Verilog Python Perl TCL Assembly Formal Verification FPGA Emulation RTL Computer Architecture Digital Logic Power Management Clock Control Testbenches Transactors Assertions
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CPU Power Management Microarchitect/RTL Engineer

Apple Inc

Waltham, MA 48 days ago $165,800–$292,400
Actively hiring Confirmed live 2 days ago Low trust Competitive pay
RTL Verilog VHDL Microarchitecture C C++ Python Perl DVFS DVFM Formal Methods Simulation Emulation Waveform Debugging Logic Design Clock Generation Asynchronous Clock Crossing
10+ yrs exp
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CPU Power Management Microarchitect/RTL Engineer

Apple Inc

Santa Clara, CA 48 days ago $184,700–$324,800
Actively hiring Confirmed live 2 days ago Low trust Above market
RTL Design Microarchitecture Verilog VHDL C C++ Python Perl DVFS DVFM Formal Methods Simulation Emulation Waveform Debugging Logic Design Power Management Clock Generation Asynchronous Clock Crossing
10+ yrs exp
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CPU Power Management Microarchitect/RTL Engineer

Apple Inc

Beaverton, OR 48 days ago
Actively hiring Confirmed live 2 days ago Low trust
RTL Verilog VHDL Microarchitecture C C++ Python Perl DVFS DVFM Formal Methods Simulation Emulation Waveform Debugging Logic Design Clock Generation Asynchronous Clock Crossing Power Integrity
10+ yrs exp
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CPU Power Management Microarchitect/RTL Engineer

Apple Inc

Santa Clara, CA 48 days ago $150,400–$277,600
Actively hiring Confirmed live yesterday Low trust Competitive pay
RTL Design Microarchitecture Verilog VHDL C C++ Python Perl DVFS DVFM Formal Methods Simulation Emulation Waveform Debugging Logic Design Power Management
3+ yrs exp
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CPU Power Management Microarchitect/RTL Engineer

Apple Inc

Santa Clara, CA 48 days ago $150,400–$277,600
Actively hiring Confirmed live yesterday Low trust Competitive pay
RTL Verilog VHDL Microarchitecture CPU Power Management DVFS DVFM C C++ Python Perl Formal Methods Simulation Emulation Waveform Debugging Logic Design
3+ yrs exp
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CPU Power Management Microarchitect/RTL Engineer

Apple Inc

Waltham, MA 48 days ago $165,800–$292,400
Actively hiring Confirmed live yesterday Low trust Competitive pay
RTL Verilog VHDL Microarchitecture C C++ Python Perl DVFS DVFM Formal Methods Simulation Emulation Logic Design Power Management
10+ yrs exp
Save

CPU Power Management Microarchitect/RTL Engineer

Apple Inc

Santa Clara, CA 48 days ago $184,700–$324,800
Actively hiring Confirmed live 2 days ago Low trust Above market
RTL Verilog VHDL Microarchitecture DVFS DVFM C C++ Python Perl Formal Methods Simulation Emulation Waveform Debugging Logic Design
10+ yrs exp
Save

CPU Power Management Microarchitect/RTL Engineer

Apple Inc

Beaverton, OR 48 days ago
Actively hiring Confirmed live yesterday Low trust
RTL Verilog VHDL Microarchitecture C C++ Python Perl DVFS DVFM Formal Methods Simulation Emulation Waveform Debugging Logic Design Clock Generation Asynchronous Clock Crossing
10+ yrs exp
Save

CPU Processor Power Management Verification Engineer

Apple Inc

Santa Clara, CA 48 days ago $150,400–$277,600
Actively hiring Confirmed live 2 days ago Trusted Above market
System Verilog Verilog UVM Python Perl Assembly Formal Verification UPF FPGA Emulation RTL Digital Logic Power Management Clock Control Random Constraint Verification
3+ yrs exp
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CPU Processor Power Management Verification Engineer

Apple Inc

Santa Clara, CA 48 days ago $129,300–$194,700
Actively hiring Confirmed live yesterday Low trust Below market
System Verilog Verilog Python Perl TCL Assembly Formal Verification FPGA Emulation RTL Computer Architecture Digital Logic Power Management Clock Control Testbenches Transactors Assertions
Save

CPU Processor Power Management Verification Engineer

Apple Inc

Santa Clara, CA 48 days ago $184,700–$324,800
Actively hiring Confirmed live yesterday Trusted Above market
System Verilog Verilog UVM Python Perl Assembly Formal Verification UPF FPGA Emulation RTL Digital Logic Power Management Clock Control
10+ yrs exp
Save

CPU Debug and Power Management Verification Engineer

Apple Inc

Beaverton, OR 48 days ago
Actively hiring Confirmed live yesterday Low trust
SystemVerilog UVM SVA Python Perl C++ Assembly AXI UPF FPGA Emulation Formal Verification Post-Silicon Debug Simulation Power Management Clock Control Hardware Trace
10+ yrs exp
Save

CPU Debug and Power Management Verification Engineer

Apple Inc

Beaverton, OR 48 days ago
Actively hiring Confirmed live yesterday Low trust
SystemVerilog UVM SVA Python C++ Assembly Perl AXI UPF FPGA Emulation Formal Verification Post-Silicon Debug Power Management Clock Control RTL Simulation
3+ yrs exp
Save