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Verilog SysVerilog C++ Python Perl TCL AgenticAI ClaudeCode Cursor CoPilot EDA ASIC Design for Testing Scan ATPG JTAG +11 more Show less

SystemVerilog UVM ASIC Emulation Formal verification Networking Python CI/CD Git JIRA Confluence Linux Docker Kubernetes +9 more Show less

UVM C++ SystemVerilog ASIC verification UCIe HBM controller Memory DFT DDR Custom HBM CI/CD +5 more Show less

Python ASIC Verification Design CI/CD

Python ASIC Verification CI/CD

Python ASIC Verification CI/CD

Python CI/CD

Python CI/CD

Python CI/CD

Python CI/CD

Python ASIC verification Test bench development

Python ASIC Design Verification Test Bench Development CI/CD

Python ASIC Verification

Python ASIC verification FPGA design Test bench development Digital ASIC verification System level testing Code coverage Functional coverage CI/CD +4 more Show less

SystemVerilog UVM Python Perl C++ ASIC Verification Emulation FormalVerification Docker CI/CD +6 more Show less

Python SystemVerilog UVM VCS Verdi Jenkins Make CI/CD Perl Docker Kubernetes Terraform AWS GCP Git GitHub Mercurial SVN Prometheus Grafana AI Machine_Learning +17 more Show less

SystemVerilog UVM Perl Python Veloce Palladium Zebu HAPS IEV VC Formal PCIe CXL Ethernet RDMA DDR TCP +11 more Show less

SystemVerilog UVM Python Perl C++ Data_center_technologies Hyperscalers AI_Networking Industry_standards Advanced_emulation Formal_verification_tools Silicon_debugging +7 more Show less

SystemVerilog UVM C++ Python Perl TCL DSP algorithms QAM Formal Verification Jasper VCFormal CI/CD Git Linux +9 more Show less

SystemVerilog UVM C++ Jasper VCFormal Python Perl TCL Makefile Git CI/CD Docker AWS Kubernetes +9 more Show less