Sr. ASIC Design Verification Engineer (Silicon Engineering)

SpaceX

Quick summary

Work type
On-site
Location
Sunnyvale, CA
Salary
$170,000–$240,000 / yr
Posted
today

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $188k
This role $205k
$142k most similar roles pay here $250k

This role pays more than 67% of similar roles. Most pay $158,850–$216,250 — the shaded band above. At the midpoint, this role pays about $205k versus about $188k for comparable roles.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 604 open roles on FindRole.

Listed pay typically runs $130,000–$155,000 across 440 roles with salary data.

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At a glance

TL;DR · Sr. ASIC Design Verification Engineer (Silicon Engineering)

The Senior ASIC Design Verification Engineer role at Silicon Engineering in Sunnyvale, CA involves designing and verifying complex integrated circuits for high-performance computing systems. This senior-level position requires expertise in creating comprehensive test plans, developing verification environments using UVM, and automating tasks with Python scripts to ensure efficient testing processes. Candidates should have a strong background in electrical or computer engineering, along with hands-on experience in SystemVerilog, UVM, and Python for automation. The ideal candidate will work on cutting-edge ASIC projects that demand rigorous verification methodologies to meet stringent performance and reliability standards at scale.

What you'll do

  • Develop and execute verification plans for complex ASIC designs.
  • Create testbenches, simulations, and validation scripts to ensure design accuracy.
  • Define coverage metrics and monitor progress towards full functional coverage.
  • Collaborate on debugging issues identified during verification phases.
  • Optimize verification environments for efficiency and scalability.

What we're looking for

  • Bachelor’s degree in electrical engineering or computer engineering
  • Experience with Python for automation
  • Strong ASIC design verification skills
  • Knowledge of U.S. Department of State ITAR requirements
  • Proven track record in silicon engineering
  • Excellent problem-solving and technical expertise

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