ASIC Design Verification Technical Leader - Acacia (hybrid)

Cisco

Hybrid

Quick summary

Work type: Hybrid
Location: Austin, TXMaynard, MA
Salary: $174,700–$253,400 / yr
Posted: 13 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $199k

This role $214k

$144k most similar roles pay here $265k

This role pays more than 66% of similar roles. Most pay $175,750–$222,425 — the shaded band above. At the midpoint, this role pays about $214k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 167 open roles on FindRole.

Listed pay typically runs $165,000–$241,400 across 167 roles with salary data.

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At a glance

TL;DR · ASIC Design Verification Technical Leader - Acacia (hybrid)

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The ASIC Design Verification Technical Lead Engineer role is a senior position within the engineering team at Cisco, focusing on next-generation 100G-1.6T coherent optical communications products. This technical leader will apply sophisticated verification techniques to ensure design quality and develop comprehensive test plans for highly complex ASICs. Day-to-day responsibilities include leading verification test benches, supervising test plan execution, collaborating with design engineers on chip-level tradeoffs, and mentoring team members. The ideal candidate should have extensive experience in object-oriented verification methodologies, SystemVerilog/UVM, and VIP development strategy, along with strong communication skills to work effectively in a fast-paced environment. Knowledge of C++ hybrid test benches, DSP algorithms, and formal verification tools like Jasper or VCFormal is preferred for this role that demands innovation and self-motivation.

Skills

SystemVerilog UVM C++ Python Perl TCL DSP algorithms QAM Formal Verification Jasper VCFormal CI/CD Git Linux

What you'll do

Lead and develop detailed verification test plans for complex ASICs.
Apply innovative techniques to verify highly sophisticated ASIC designs.
Supervise the execution of verification test benches by team members.
Mentor teammates on advanced verification methodologies and technologies.
Work with design engineers to make chip-level design tradeoffs.
Review and improve design verification coding and coverage metrics.
Develop and incorporate cutting-edge test technologies and processes.

What we're looking for

Bachelor's or Master’s degree in a relevant engineering field with 12+ years of ASIC verification experience.
Proficiency in SystemVerilog/UVM and VIP development strategy.
Ability to lead and develop comprehensive test plans and verification test benches.
Experience applying innovative verification techniques to complex designs.
Strong technical leadership, mentoring skills, and ability to work independently.
Knowledge of formal verification methodologies and tools like Jasper or VCFormal.

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