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SystemVerilog RTL CDC RDC SDC VCS SVA Static Glitch Analysis +3 more Show less

SystemVerilog UVM Perl Python PCIe CXL Ethernet AHB AXI DDR MMU Veloce HAPS FormalVerification iEV VC Formal +11 more Show less

Cadence Sigrity Ansys HFSS Keysight ADS Cadence APD Ansys EM SPICE Transmission Line Theory Electromagnetics Scattering Parameters Impedance Network Analysis 56G PAM4 SerDes Channel Modeling BER Prediction HBM UCIe CoWoS EMIB Vector Network Analysis IBIS +14 more Show less

Jtag Scan BIST ATPG TestMax Tetramax Tessent PrimeTime SystemVerilog Verilog EDA DFT CAD StaticTimingAnalysis PostSiliconDebug +10 more Show less

SystemVerilog UVM Python Perl Emulation FormalVerification SiliconBring-up Post-siliconDebug Scripting DataCenterTechnologies AINetworking ASICVerificationMethodologies +7 more Show less

Verilog SystemVerilog Python Perl TCL shell programming CDC Spyglass digital design principles microarchitecture concepts buffering scheduling architectures +7 more Show less

Jtag Scan BIST ATPG TestMax Tetramax Tessent PrimeTime VCS Verilog System Verilog Gate level simulation DFT EDA tools Test Static Timing Analysis CI/CD +11 more Show less

SystemVerilog UVM C++ Python Perl TCL DSP algorithms QAM Formal Verification Jasper VCFormal CI/CD Git Linux +9 more Show less

SystemVerilog UVM C++ Jasper VCFormal Python Perl TCL Makefile Git CI/CD Docker AWS Kubernetes +9 more Show less

SystemVerilog UVM Linux C C++ Python Perl Veloce Palladium Zebu HAPS Networking Dashboard_management CI/CD +9 more Show less

SystemVerilog UVM Linux C++ Python Perl Veloce Palladium Zebu HAPS CI/CD Networking Dashboard_management Emulation_platforms +9 more Show less

ASIC STA Hyperscale hierarchical analysis parasitic stitching IO budgeting flat parasitic extraction timing constraints timing closure ECO on-chip variation AOCV POCV voltage temperature aging-based timing derates Synopsys DC/DCG/FC Formality Cadence LEC Star-RCXT Quantus Synopsys Primetime PTPX Tweaker PrimeClosure Tempus TCL Perl Python +24 more Show less

Tcl Python Perl Verilog TestMax Tetramax Tessent JTAG ATPG PostgreSQL Git CI/CD Docker Kubernetes AWS GCP Azure SVN Mercurial +14 more Show less

Tcl Python Perl shell scripting EDA DFT toolchain Synopsys TestMAX Synopsys VCS Siemens Tessent LSF AI/ML techniques data analytics tools pandas dashboards visualization tools large-scale regression systems distributed job management STIL +12 more Show less

Python Tcl C++ Siemens_Tessent Synopsys RTL Verilog System_Verilog DFT ATPG SDF Scan_Insertion Memory_BIST Logic_BIST ATE_testers +10 more Show less

Tcl Python Perl Jtag Scan BIST Memory BIST Boundary Scan RTL Lint CDC Post-silicon test bring up Debugging Silicon validation Yield support DFT DFx In-system test Debug and diagnostics +14 more Show less

Python C/C++ MATLAB Keysight ADS Synopsys HSPICE Cadence IBIS-AMI Linux Perl TCL PAM4 ASIC SoC EDA SI simulation tools +10 more Show less

SystemVerilog UVM Python Perl TCL Shell SerDes D2D_PHY_IP ODSP Ethernet UCIE UAL SPI I2C Formal_Verification Verilog Veloce HAPS Emulation_Pods +14 more Show less