ASIC Design Verification Engineer, Technical Leader

Cisco

Quick summary

Work type: On-site
Location: San Jose, CA
Salary: $183,800–$263,600 / yr
Posted: 2 days ago
Closes: Jul 31, 2026
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $196k

This role $224k

$139k most similar roles pay here $277k

This role pays more than 80% of similar roles. Most pay $174,806–$216,562 — the shaded band above. At the midpoint, this role pays about $224k versus about $196k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 186 open roles on FindRole.

Listed pay typically runs $165,000–$241,400 across 186 roles with salary data.

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At a glance

TL;DR · ASIC Design Verification Engineer, Technical Leader

Role Posting Log in to save

As an ASIC design verification engineer at Cisco in San Jose, CA, you will join the Silicon One development team to ensure high-quality verification of complex ASICs through simulation, emulation, and bring-up phases. Your daily tasks include maintaining and enhancing existing DV environments, constructing comprehensive test benches with scoreboards and agents, developing detailed test plans and cases, debugging regression failures, and ensuring thorough coverage through code and functional reviews. You will leverage AI tools to innovate methods for improving verification quality and collaborate closely with cross-functional teams. The ideal candidate has extensive experience in System Verilog and UVM methodology, building test benches from scratch, and scripting skills in Perl or Python. Knowledge of protocols like PCIe, CXL, Ethernet, AHB/AXI, DDR, and MMU is beneficial, as well as familiarity with Veloce/HAPS emulation platforms and formal verification tools.

Skills

SystemVerilog UVM Perl Python PCIe CXL Ethernet AHB AXI DDR MMU Veloce HAPS FormalVerification iEV VC Formal

What you'll do

Maintain and enhance existing DV environments.
Construct test bench components for new ASIC blocks.
Develop test plans and cases to achieve verification closure.
Ensure comprehensive functional coverage through code reviews.
Utilize AI tools to innovate design verification processes.

What we're looking for

8+ years of experience in ASIC design verification with a Bachelor's degree or 6+ years with a Master's.
Proficient in System Verilog and UVM methodology for test bench construction and maintenance.
Experience verifying complex blocks, clusters, and top-level designs for ASIC/SoC.
Hands-on skills in building test benches from scratch using System Verilog constraints, structures, and classes.
Expertise in functional coverage and constrained random DV environments to ensure complete verification coverage.
Scripting experience with Perl or Python for automation and process improvement.