ASIC Design Verification Engineer, Technical Leader

Cisco

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: San Jose, CA
Salary: $186,900–$267,700 / yr
Posted: 38 days ago
Freshness: Confirmed live yesterday
Closes: Sep 30, 2026
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $194k

This role $227k

$136k most similar roles pay here $282k

This role pays more than 78% of similar roles. Most pay $168,125–$218,950 — the shaded band above. At the midpoint, this role pays about $227k versus about $194k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 196 open roles on FindRole.

Listed pay typically runs $167,700–$245,200 across 196 roles with salary data.

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At a glance

TL;DR · ASIC Design Verification Engineer, Technical Leader

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As an ASIC Design Verification Engineer, Technical Leader within the Silicon One development organization, you will join the Common Hardware Group to support the creation of innovative hardware platforms for switching, routing, and wireless products. You will collaborate with cross-functional teams to verify the ASIC through simulation, emulation, and bring-up phases. Your daily responsibilities include maintaining and enhancing existing verification environments, constructing test benches with scoreboards and agents, writing test plans, and debugging regression failures to achieve module verification closure. You will utilize SystemVerilog, UVM methodology, and Perl or Python scripting to ensure full coverage through constrained random environments. The role also involves using AI tools to improve design verification processes. Relevant domain expertise may include protocols such as PCIe, CXL, Ethernet, AHB/AXI, DDR, MMU, and experience with Veloce, HAPS, or formal verification tools.

Skills

System Verilog UVM ASIC SoC Python Perl PCIe CXL Ethernet AHB AXI DDR Formal Verification Veloce HAPS Simulation Emulation

What you'll do

Maintain and enhance existing ASIC design verification environments.
Construct test benches including scoreboards, agents, sequencers, and monitors for new blocks.
Write comprehensive test plans and develop specific test cases for module verification.
Debug regression failures and drive projects toward successful module verification closure.
Ensure complete verification coverage through the implementation and review of code and functional coverage.
Utilize AI tools to develop innovative methods and processes to improve design verification quality.
Verify the ASIC across simulation, emulation, and hardware bring-up phases.

What we're looking for

A Bachelor's degree with or a Master's degree with relevant experience is required.
Experience with SystemVerilog and UVM methodology is required.
Prior experience verifying complex blocks, clusters, and/or top-level for ASIC/SoC is required.
Hands-on experience building test benches from scratch using SystemVerilog constraints, structures, and classes is required.
Experience with functional coverage and constrained random verification environments is required.
Proficiency in Perl and/or Python scripting is required.
Domain experience in protocols such as PCIe, CXL, Ethernet, AHB/AXI, DDR, or MMU is preferred.
Knowledge of formal verification (iev/vc formal) and experience with Veloce/HAPS are preferred.

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