ASIC DFT Technical Lead

Cisco

Remote

Quick summary

Work type: Remote
Location: San Jose, CA
Salary: $210,600–$305,100 / yr
Posted: 46 days ago
Closes: Jul 3, 2026
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $192k

This role $258k

$135k most similar roles pay here $323k

This role pays more than 97% of similar roles. Most pay $168,125–$216,250 — the shaded band above. At the midpoint, this role pays about $258k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 171 open roles on FindRole.

Listed pay typically runs $165,000–$241,400 across 171 roles with salary data.

Most-posted roles

View all roles at Cisco

At a glance

TL;DR · ASIC DFT Technical Lead

Apply Now Log in to save

As an ASIC implementation engineer at Cisco's Silicon One development organization in San Jose, CA, you will lead the DFT/DFx and quality process through the early product life cycle, including architecture definitions, RTL implementation, and quality checks. You will develop comprehensive DFT & DFx solutions for ATE screening, in-system test, debug, and diagnostics needs, and work on innovative hardware DFT & test strategies for new silicon devices. Responsibilities include identifying DFT challenges, developing cross-functional solution plans, and leading a team to deliver implementations on schedule. The role requires expertise in JTAG protocols, scan and BIST architectures, post-silicon test bring-up, debug analysis, and RTL QA checks. Proficiency in scripting languages such as Tcl, Python, and Perl is essential for this high-impact position focused on cutting-edge networking chips.

Skills

Tcl Python Perl Jtag Scan BIST Memory BIST Boundary Scan RTL Lint CDC Post-silicon test bring up Debugging Silicon validation Yield support DFT DFx In-system test Debug and diagnostics

What you'll do

Develop comprehensive DFT and DFx solutions for ATE screening and in-system testing.
Lead RTL implementation from architecture specifications with required quality checks.
Innovate hardware DFT strategies for new silicon devices, including bare die and stacked die.
Identify DFT challenges and develop cross-functional solution plans with a team of engineers.
Conduct post-silicon validation and support production yield and DPPM.

What we're looking for

At least 10+ years of ASIC hardware development experience.
Expertise in DFT/DFx solutions and RTL implementation from architecture specifications.
Experience with JTAG protocols, Scan, BIST architectures, memory BIST, and boundary scan.
Post-silicon test bring-up, debug, and failure analysis skills.
Knowledge of RTL QA checks including lint and CDC.