ASIC Technical Lead, DFT

Cisco

Remote

Quick summary

Work type: Remote
Location: Remote
Salary: $210,600–$305,100 / yr
Posted: 6 days ago
Closes: Aug 25, 2026

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $191k

This role $258k

$128k most similar roles pay here $324k

This role pays more than 95% of similar roles. Most pay $165,087–$216,250 — the shaded band above. At the midpoint, this role pays about $258k versus about $191k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 186 open roles on FindRole.

Listed pay typically runs $165,000–$241,400 across 186 roles with salary data.

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At a glance

TL;DR · ASIC Technical Lead, DFT

Role Posting Log in to save

As an ASIC Implementation Technical Lead at Cisco Silicon One in San Jose, CA, you will lead the Design-for-Test (DFT) process for next-generation networking chips, collaborating with front-end RTL and backend physical design teams to ensure robust DFT features are integrated early in the design cycle. Your daily tasks include developing innovative DFT IP, enabling test logic integration across various phases of implementation and post-silicon validation, and driving re-usable test strategies for new silicon devices. This role requires expertise in JTAG protocols, scan and BIST architectures, ATPG, and EDA tools like TestMax, Tetramax, Tessent, and PrimeTime, along with experience in Verilog design, functional verification, and post-silicon validation using DFT patterns.

Skills

Jtag Scan BIST ATPG TestMax Tetramax Tessent PrimeTime SystemVerilog Verilog EDA DFT CAD StaticTimingAnalysis PostSiliconDebug

What you'll do

Implement Hardware Design-for-Test (DFT) features supporting automated test equipment and in-system testing.
Develop innovative DFT IP and integrate it with RTL for full chip design.
Collaborate with design and verification teams to validate Test logic throughout implementation phases.
Lead the creation of re-usable test and debug strategies for new silicon device models.
Craft solutions and debug issues independently, requiring minimal mentorship.

What we're looking for

At least 10 years of experience in Electrical or Computer Engineering.
Expertise in JTAG protocols, Scan and BIST architectures, including memory BIST and boundary scan.
Proficiency with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime.
Experience in developing custom DFT logic and IP integration.
Strong background in system verification using System Verilog and Logic Equivalency checking.

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