ASIC Technical Leader- DFT

Cisco

Remote Actively hiring
Remote, USA · San Jose, CA Posted 23 days ago $183,800–$263,600 / year
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At a glance

AI generated

TL;DR

As an ASIC Implementation Technical Lead with a focus on Design-for-Test in the Silicon One development organization at Cisco, you will manage high-performance ASIC definitions and architectures while overseeing reusable code applications to promote design efficiencies. Your daily responsibilities include defining verification strategies, coordinating with stakeholders for integration into physical design and design validation flows, and owning infrastructure and testing environments. You will lead technical expertise within a physical design function, interface with vendors on full chip timing closure, and develop multiple solutions for test vehicles. The role requires extensive experience in JTAG protocols, scan insertion, BIST architectures, ATPG, EDA tools like TestMax and Tessent, gate-level simulation, and post-silicon validation. Strong scripting skills in Tcl, Python, or Perl are essential, along with a background in Verilog design for custom DFT logic integration and functional verification.

Skills

Tcl Python Perl Verilog TestMax Tetramax Tessent JTAG ATPG PostgreSQL Git CI/CD Docker Kubernetes AWS GCP Azure SVN Mercurial

What you'll do

  • Defines and oversees the architecture of high-performance ASICs.
  • Manages DFT requirements and drives them through the entire design cycle.
  • Leads the creation of reusable code to enhance efficiency in new designs.
  • Coordinates with stakeholders to integrate DFT into physical design flows.
  • Applies and drives design methodologies from conception to production phases.
  • Interfaces with vendors on full chip timing closure, PI, and PV activities.
  • Develops test vehicles and performs verification and validation for post-silicon.

What we're looking for

  • Bachelor's or Master’s Degree in Electrical or Computer Engineering with at least 10 years of experience.
  • Experience with JTAG protocols, scan insertion, BIST architectures, and memory BIST.
  • Proficiency in ATPG and EDA tools like TestMax, Tetramax, Tessent for test static timing analysis.
  • Expertise in gate level simulation and post-silicon validation and debug processes.
  • Strong scripting skills in Tcl, Python, or Perl.

Market check

Salary context

This $183,800–$263,600 range sits above 75% of similar postings on FindRole.

Peer median band

$152,400–$231,300

Median floor and ceiling across peers.

Typical midpoint (25–75%)

$160,325–$223,712

Middle half of comparable postings.

Based on 240 comparable postings.

* 240 is the maximum number of comparable postings sampled.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 103 open roles on FindRole.

Listed pay typically runs $165,000–$241,400 across 103 roles with salary data.

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