ASIC Packaging Signal Power Integrity Hardware Engineering Technical Lead

Cisco

Remote

Quick summary

Work type
Remote
Location
San Jose, CARTPActon, MADallas, TXTempe, AZ
Salary
$183,800–$263,600 / yr
Posted
5 days ago
Closes
Sep 25, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $191k
This role $224k
$133k most similar roles pay here $278k

This role pays more than 84% of similar roles. Most pay $169,250–$212,687 — the shaded band above. At the midpoint, this role pays about $224k versus about $191k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 186 open roles on FindRole.

Listed pay typically runs $165,000–$241,400 across 186 roles with salary data.

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At a glance

TL;DR · ASIC Packaging Signal Power Integrity Hardware Engineering Technical Lead

Role Posting Log in to save

As a Signal and Power Integrity Technical Lead at Cisco in San Jose, CA, you will join a specialized ASIC team focused on advanced IC package design and heterogeneous system integration using cutting-edge 2.5D fanout technologies. Your role involves developing and documenting ultra-high-speed signaling design rules to meet performance goals for various platforms, analyzing signal and power integrity issues, collaborating with layout teams to optimize solutions, and defining processes for complex ASIC/package developments. You will also mentor junior engineers, lead technical discussions on chip architecture, and promote continuous improvement across multi-disciplined engineering teams. The ideal candidate has extensive experience in high-speed design principles, proficiency with EDA tools like Cadence Sigrity and Ansys HFSS, and a strong background in circuit analysis using SPICE. This role requires expertise in 56G PAM4 SerDes architectures and channel modeling, as well as familiarity with advanced packaging technologies such as CoWoS and EMIB designs.

Skills

Cadence Sigrity Ansys HFSS Keysight ADS Cadence APD Ansys EM SPICE Transmission Line Theory Electromagnetics Scattering Parameters Impedance Network Analysis 56G PAM4 SerDes Channel Modeling BER Prediction HBM UCIe CoWoS EMIB Vector Network Analysis IBIS

What you'll do

  • Develop and document design rules for ultra-high-speed signaling to meet product goals.
  • Analyze substrate signal integrity and power integrity, collaborating with layout teams.
  • Design and develop ASIC packages for high-volume release, including post-layout extraction.
  • Define processes and methods for complex ASIC/package developments.
  • Lead chip architecture discussions and review intricate IC designs.
  • Mentor junior engineers and support the signal integrity team on technical specifications.
  • Promote a culture of design reviews and continuous improvement across engineering teams.

What we're looking for

  • Bachelor's degree in Electrical Engineering with 8+ years of signal and power integrity experience.
  • Expertise in high-speed design principles including Transmission Line Theory and channel modeling.
  • Proficiency in SI/PI simulations using EDA tools like Cadence Sigrity, Ansys HFSS, and Keysight ADS.
  • Experience conducting detailed layout reviews and physical design validation with tools such as Cadence APD.
  • Working knowledge of SPICE for circuit-level analysis and performance validation.

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