ASIC Engineering Technical Lead - DFT

Cisco

Quick summary

Work type: On-site
Location: San Jose, CAAustin, TXMaynard, MassachusettsSeattle, WACarlsbad, CA
Salary: $183,800–$263,600 / yr
Posted: 46 days ago
Closes: Jun 30, 2026
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $193k

This role $224k

$139k most similar roles pay here $277k

This role pays more than 81% of similar roles. Most pay $169,250–$216,250 — the shaded band above. At the midpoint, this role pays about $224k versus about $193k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 167 open roles on FindRole.

Listed pay typically runs $165,000–$241,400 across 167 roles with salary data.

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At a glance

TL;DR · ASIC Engineering Technical Lead - DFT

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Join Acacia at Cisco as an ASIC Engineering Technical Leader specializing in Design-for-Test for next-generation optical interconnect products. You will lead the development of DFT solutions using Siemens Tessent or Synopsys tools, implementing hierarchical test flows and generating ATPG patterns for various fault models. Responsibilities include evaluating design readiness through RTL and physical design checks, integrating DFT fabrics within subsystems, and performing gate-level simulations. The role requires expertise in Python, Tcl, and C++ for automation and data analysis, alongside a deep understanding of advanced silicon processes and high-speed low-power technology nodes. Ideal candidates have extensive experience in ASIC development and DFT setup across multi-100G to 1.6T coherent optical communications products.

Skills

Python Tcl C++ Siemens_Tessent Synopsys RTL Verilog System_Verilog DFT ATPG SDF Scan_Insertion Memory_BIST Logic_BIST ATE_testers

What you'll do

Lead implementation of SSN and hierarchical test flow DFT architectures using Siemens Tessent or Synopsys tools.
Generate ATPG test patterns for various fault models and drive scan-based diagnosis methodology for silicon failure debug.
Evaluate design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools.
Integrate and verify DFT fabrics and IP within subsystems, ensuring proper functionality and reliability.
Develop test scripts and automate processes using programming languages such as Python, Tcl, or C++.

What we're looking for

Prior experience working with ASICs and implementing DFT architectures.
Expertise in scan insertion, compression/decompression logic, and memory/logic BIST.
Experience generating ATPG test patterns for various fault models.
Ability to integrate and verify Design for Test (DFT) fabrics within subsystems.
Proficiency in using Siemens Tessent or Synopsys tools for DFT implementation.

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