ASIC Design Verification Technical Leader

Cisco

Confirmed live 2 days ago High trust

Remote

Quick summary

Work type: Remote
Location: Carlsbad, CA
Salary: $163,600–$234,600 / yr
Posted: 53 days ago
Freshness: Confirmed live 2 days ago
Closes: Sep 30, 2026
Nearby: 20 roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $196k

This role $199k

$137k most similar roles pay here $245k

This role pays more than 56% of similar roles. Most pay $168,500–$223,175 — the shaded band above. At the midpoint, this role pays about $199k versus about $196k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 196 open roles on FindRole.

Listed pay typically runs $167,700–$245,200 across 196 roles with salary data.

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At a glance

TL;DR · ASIC Design Verification Technical Leader

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As an ASIC Design Verification Technical Leader within the Client Optics Group, you will drive verification for silicon photonics driver integrated circuits supporting 100/200/400G per Lambda solutions. You will define and lead verification methodologies across multiple projects, coordinate activities across various sites, and mentor engineers to improve technical skills. Your daily responsibilities include leading block and chip level verification for high-speed IPs like SerDes, D2D PHY, and integrated drivers, while reviewing specifications to influence architecture for testability. The role requires expertise in SystemVerilog, UVM, and hardware description languages like Verilog. You will also utilize scripting tools such as Python, Perl, TCL, or Shell Scripts, and leverage emulation platforms like Veloce or HAPS. This position addresses the technical challenge of developing high-speed optical transceivers and modules for next-generation data center architectures.

Skills

System Verilog UVM Verilog Python Perl TCL Formal Verification ASIC Design Verification Ethernet UCIE SPI I2C Veloce HAPS SerDes PAM4

What you'll do

Define and lead verification methodologies and standards across multiple projects and sites.
Lead block and chip level verification for high-speed IPs including SerDes, D2D, and integrated drivers.
Review specifications and participate in design reviews to influence architecture for testability and efficiency.
Mentor and coach verification engineers to improve technical skills and execution.
Debug complex silicon and system-level issues during the product bring-up phases.
Support post-silicon bring-up while optimizing integration and performance.
Develop scalable, reusable, and coverage-driven verification environments using UVM.

What we're looking for

A Bachelor's degree in Electrical or Computer Engineering with 8+ years of ASIC Design Verification experience is required.
A Master's degree in Electrical or Computer Engineering with 6+ years of ASIC Design experience is required.
A PhD in Electrical or Computer Engineering with 3 years of ASIC Design Verification experience is required.
Experience in System Verilog, UVM, and verification methodologies is required.
Experience owning and delivering verification for large-scale SoCs or subsystems is required.
Experience leading verification teams or projects is required.
Proficiency in scripting and automation using Python, Perl, TCL, or Shell Scripts is required.
Experience with hardware description languages (HDLs), formal verification, and emulation/prototyping platforms is preferred.

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