ASIC Link Modeling Technical Leader

Cisco

Confirmed live 2 days ago High trust
Remote

Quick summary

Work type
Remote
Location
Carlsbad, CA
Salary
$189,300–$271,500 / yr
Posted
53 days ago
Freshness
Confirmed live 2 days ago
Closes
Sep 30, 2026
Nearby
20 roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $204k
This role $230k
$147k most similar roles pay here $285k

This role pays more than 74% of similar roles. Most pay $177,250–$231,075 — the shaded band above. At the midpoint, this role pays about $230k versus about $204k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 196 open roles on FindRole.

Listed pay typically runs $167,700–$245,200 across 196 roles with salary data.

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At a glance

TL;DR · ASIC Link Modeling Technical Leader

Role Posting Log in to save

The ASIC Link Modeling Technical Leader joins the Client Optics Group to develop and test advanced pluggable and Co-packaged Optics for high-speed data center networking. This role involves creating system-level behavioral models and comprehensive link simulations for silicon photonics systems, specifically targeting 100/200/400G per Lambda solutions. The candidate will perform link budget analysis, channel modeling, and statistical simulations to evaluate jitter, noise, crosstalk, and bit error rates across transmit and receive paths. Key responsibilities include optimizing transceiver architectures like FFE, CTLE, and DFE while correlating pre-silicon models with post-silicon lab measurements. Required skills include proficiency in Python, C/C++, and MATLAB for behavioral modeling, along with expertise in high-speed communication theory, SerDes, and DSP fundamentals. The role utilizes EDA and SI tools such as Keysight ADS, Synopsys HSPICE, and Cadence to solve complex signal integrity challenges.

Skills

Python C/C++ MATLAB IBIS-AMI ADS HSPICE Cadence Linux Perl TCL SerDes PAM4 DSP Ethernet Signal Integrity ASIC SoC

What you'll do

  • Develop system-level behavioral models and comprehensive link simulations for silicon photonics systems.
  • Perform link budget analysis and statistical simulations to evaluate jitter, noise, crosstalk, and bit error rate.
  • Define and optimize transceiver architectures including TX/RX equalization, clock recovery, and DSP algorithms.
  • Debug complex link simulations to identify architectural bottlenecks and validate design performance.
  • Correlate pre-silicon models with post-silicon lab measurements to ensure hardware accuracy.
  • Develop IBIS-AMI models and create technical documentation to support product release.
  • Automate analysis and modeling tasks using Python, C/C++, or MATLAB.

What we're looking for

  • Bachelor's degree plus 12 years experience, Master's plus 8 years, or PhD plus 5 years of ASIC link modeling experience.
  • Proficiency in Python, C/C++, and MATLAB for behavioral model development and automated analysis.
  • Strong understanding of high-speed communication theory, transmission line theory, SerDes, Ethernet, D2D PHY protocols, and DSP fundamentals.
  • Experience with EDA and SI simulation tools such as Keysight ADS, Synopsys HSPICE, or Cadence.
  • Experience with optical DSP (ODSP), integrated transceiver features, and PAM4 modulation techniques.
  • Familiarity with IBIS-AMI model development for signal integrity simulations.
  • Experience in Linux-based environments with scripting automation using Perl or TCL.
  • Knowledge of ASIC/SoC design flow and multi-functional impacts on link performance like packaging, PCB, and optics.

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