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Python PCIe SerDes Ethernet DDR5 USB_3_x SGMII BERT oscilloscopes logic_analyzers VNAs protocol_analyzers multimeters high_speed_interfaces signal_integrity power_integrity waveform_analysis eye_diagrams jitter_analysis BER_measurements thermal_testing lab_automation schematics_and_layout_files networking_fundamentals packet_based_systems +20 more Show less

Python Perl Make Shell_scripting AI_frameworks RTL Functional_verification Formal_verification Physical_design CI/CD EDA_tools Kubernetes Docker Terraform AWS Grafana Prometheus +12 more Show less

SystemVerilog UVM C++ Python Perl Formal Verification Coverage Metrics X-propagation DFT/IST Tegra GPU CI/CD +7 more Show less

SystemVerilog UVM ASIC Emulation Formal verification Networking Python CI/CD Git JIRA Confluence Linux Docker Kubernetes +9 more Show less

TCL Python Perl UPF CPF LEC MCMM_STA DFT SerDes PCIe CXL C2C Die-to-Die RTL-to-GDSII CTS EMIR ECO EDA_tool_suites automation_scripting +14 more Show less

SystemVerilog UVM Perl Python Veloce Palladium Zebu HAPS IEV VC Formal PCIe CXL Ethernet RDMA DDR TCP +11 more Show less

ASIC FPGA RTL Synthesis Functional Verification Physical Layout Emulation Program Management Milestone Planning Risk Management Dependency Tracking Delivery Execution Silicon Engineering Hardware Systems Software Development Operations Management Cross-Functional Collaboration Technical Leadership Product Management CI/CD +15 more Show less

Verilog SystemVerilog Python Perl TCL shell programming CDC Spyglass digital design principles microarchitecture concepts buffering scheduling architectures +7 more Show less

Jtag Scan BIST ATPG TestMax Tetramax Tessent PrimeTime VCS Verilog System Verilog Gate level simulation DFT EDA tools Test Static Timing Analysis CI/CD +11 more Show less

Keysight ADS Ansys HFSS Cadence APD SPICE Python Raptor-X MATLAB Vector Network Analysis IBIS 56G PAM4 SerDes HBM UCIe CoWoS EMIB 2.5D ASIC packaging +11 more Show less

SystemVerilog UVM Linux C C++ Python Perl Veloce Palladium Zebu HAPS Networking Dashboard_management CI/CD +9 more Show less

SystemVerilog UVM Linux C++ Python Perl Veloce Palladium Zebu HAPS CI/CD Networking Dashboard_management Emulation_platforms +9 more Show less

SystemVerilog VLSI RTL HDL Physical Design Computer Architecture AI GPU Deep Learning CI/CD +4 more Show less

TCL Perl Python Cadence_Innovus Synopsys_ICC2 Synopsys_Design_Complier Synopsys_Formality Cadence_Logic_Equivalence_Checker Tempus Synopsys_ICV Mentor_Calibre Static_Timing_Analysis Hierarchical_floor_planning Clock_and_power_distribution Global_signal_and_I_O_planning Physical_verification_DRC/LVS Block_level_EMIR_closure ECO_strategies RTL_to_GDSII_implementation +14 more Show less

ASIC STA Hyperscale hierarchical analysis parasitic stitching IO budgeting flat parasitic extraction timing constraints timing closure ECO on-chip variation AOCV POCV voltage temperature aging-based timing derates Synopsys DC/DCG/FC Formality Cadence LEC Star-RCXT Quantus Synopsys Primetime PTPX Tweaker PrimeClosure Tempus TCL Perl Python +24 more Show less

Verilog SystemVerilog

SystemVerilog UVM ASIC Linux C C++ Python Perl Networking Formal verification +5 more Show less

SystemVerilog UVM VCS Verdi Perl Python C++ UPF DFT Machine_Learning ASIC_design_flow +6 more Show less