Senior ASIC Design Verification Engineer - LPU

Nvidia

Remote

Quick summary

Work type: Remote
Location: CA, CA · TX, TX
Salary: $168,000–$264,500 / yr
Posted: 86 days ago

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $190k

This role $216k

$127k most similar roles pay here $279k

This role pays more than 79% of similar roles. Most pay $163,950–$216,250 — the shaded band above. At the midpoint, this role pays about $216k versus about $190k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 563 open roles on FindRole.

Listed pay typically runs $168,000–$264,500 across 556 roles with salary data.

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At a glance

TL;DR · Senior ASIC Design Verification Engineer - LPU

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NVIDIA seeks an experienced ASIC Verification Engineer to join its globally recognized team dedicated to advancing inference accelerator technology. In this role, you will verify the design and implementation of high-performance processor elements for programmable compute and graphics functionality, collaborating closely with architects and designers. Key responsibilities include developing verification infrastructure, defining verification scope, and implementing automated verification flows using advanced methodologies such as UVM and random stimulus techniques. The ideal candidate holds a Bachelor’s degree in EE, CS, or CE, with 8+ years of relevant experience in building block and SoC level testbenches, SystemVerilog expertise, and proficiency in design tools like VCS and Verdi. Knowledge of machine learning applications in ASIC verification is advantageous, as is familiarity with Perl/Python and C/C++ programming for enhanced automation and efficiency.

Skills

SystemVerilog UVM VCS Verdi Perl Python C++ UPF DFT Machine_Learning ASIC_design_flow

What you'll do

Verify the design and implementation of inference accelerator using advanced methodologies.
Define verification scope, develop infrastructure, and ensure correctness of ASIC design.
Implement automated verification flows to enhance productivity and efficiency.
Collaborate with architects and designers to accomplish verification tasks effectively.
Stay updated on trends in ASIC design verification and apply innovative techniques.

What we're looking for

8+ years of relevant industry experience in ASIC verification
Strong background in SystemVerilog and Universal Verification Methodology (UVM)
Experience with design and verification tools such as VCS, Verdi
Expertise in verification using random stimulus and functional coverage
Knowledge of applying machine learning to ASIC verification flow
Perl/Python and C/C++ programming language experience preferred

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