ASIC Design Verification Engineer

Cisco

Remote

Quick summary

Work type
Remote
Location
San Jose, CA
Salary
$165,000–$241,400 / yr
Posted
67 days ago
Closes
Jul 3, 2026

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $191k
This role $203k
$136k most similar roles pay here $253k

This role pays more than 65% of similar roles. Most pay $165,250–$216,250 — the shaded band above. At the midpoint, this role pays about $203k versus about $191k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 174 open roles on FindRole.

Listed pay typically runs $165,000–$241,400 across 174 roles with salary data.

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At a glance

TL;DR · ASIC Design Verification Engineer

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Join the Common Hardware Group (CHG) as an ASIC Design Verification Engineer, where you will contribute to the design verification of high-end switching products for Cisco’s Silicon One architecture. Your daily tasks will involve developing simulation models and test plans, creating comprehensive testbenches with components like scoreboards and agents, and collaborating closely with hardware and software teams. You’ll need expertise in System Verilog/UVM, ASIC design and verification processes, and experience with multi-chip/system simulations. Preferred qualifications include post-silicon lab bring-up, Linux, C/C++, Python/Perl, and networking knowledge. This role demands a Bachelor’s degree plus 7 years or equivalent experience, shaping groundbreaking solutions for enterprises worldwide.

Skills

SystemVerilog UVM ASIC Linux C C++ Python Perl Networking Formal verification

What you'll do

  • Participate in ASIC design verification for high-end switching products.
  • Develop simulation models, test plans, and direct/random tests for designs.
  • Construct testbench components including scoreboards, agents, sequencers, and monitors.
  • Perform end-to-end verification of design blocks and top-level integration.
  • Analyze performance and conduct multi-chip/system simulations during development.

What we're looking for

  • Bachelor's degree with 7+ years or Master's with 4+ years of related experience in electrical/computer engineering.
  • Proficient in System Verilog/UVM for ASIC design verification.
  • Experience in full chip level verification and debugging methodologies.
  • Collaborative work with hardware, software designers, and vendors.
  • Construct testbenches including scoreboards, agents, sequencers, and monitors.
  • Preferred: Post-silicon lab bring-up experience and formal verification expertise.

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