Senior LPU ASIC Engineer

Nvidia

Remote

Quick summary

Work type
Remote
Location
Santa Clara, CA
Salary
$136,000–$218,500 / yr
Posted
2 days ago

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $181k
This role $177k
$126k most similar roles pay here $228k

This role pays more than 57% of similar roles. Most pay $155,750–$205,750 — the shaded band above. At the midpoint, this role pays about $177k versus about $181k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 985 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 971 roles with salary data.

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At a glance

TL;DR · Senior LPU ASIC Engineer

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As a Senior LPU ASIC Engineer at NVIDIA, you will join a cutting-edge team focused on advancing AI technology through innovative chip design. Your daily responsibilities include full-flow ownership of synthesis, floorplanning, place & route, and timing constraints for complex SoCs, as well as cross-functional optimization with IP, front-end logic design, and architecture teams to enhance PPA and resolve architectural bottlenecks. You will also lead tapeout execution and methodology innovation by collaborating with CAD teams to implement automated enhancements that improve efficiency and design cycle times. The ideal candidate has a B.S. in Electrical/Computer Engineering or equivalent experience, with expertise in full-flow physical design, low-power methodologies, clock tree synthesis, and EDA tool proficiency, including scripting languages like TCL, Python, and Perl. Specialized knowledge in high-speed IP integration is beneficial for this role at the forefront of AI technology development.

Skills

TCL Python Perl UPF CPF LEC MCMM_STA DFT SerDes PCIe CXL C2C Die-to-Die RTL-to-GDSII CTS EMIR ECO EDA_tool_suites automation_scripting

What you'll do

  • Lead full-flow ownership for Synthesis, floorplanning, place & route, timing constraints, UPF, and LEC.
  • Optimize IP integration with front-end logic design teams to enhance PPA and resolve architectural bottlenecks.
  • Execute tapeout by leading design closure and ensuring 100% verification compliance for GDSII handoff.
  • Innovate EDA methodologies in collaboration with CAD teams to automate enhancements improving PPA and efficiency.
  • Master clock tree synthesis, sign-off timing analysis, and complex constraint-driven CTS methodologies.

What we're looking for

  • B.S. in Electrical/Computer Engineering or equivalent with 5+ years of industry experience.
  • Proven track record of full-flow physical design for large-scale SoCs at advanced nodes.
  • Deep expertise in low-power design, UPF/CPF, and formal equivalency checks (LEC).
  • Expertise in clock tree synthesis, CTS methodologies, and sign-off timing analysis.
  • Demonstrated ability to optimize power, performance, and area across the entire physical design cycle.
  • Strong command of power grid design, EMIR analysis, and ECO generation for robust silicon integrity.
  • Proficiency in scripting (TCL, Python, Perl) for automating end-to-end physical design flows.

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