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DFT SoC Architecture RTL Design Verilog UVM Post-Silicon Validation ATE Python Perl Tcl STA Place & Route Power Optimization Fuse Controller DFT IP Verification Synthesis +12 more Show less

ASIC Design RTL Design Logic Synthesis Timing Analysis SoC Integration Python Perl C++ UCIe Digital Design Verification Methodology Boot Controllers Reset Controllers Memory Controllers DMA +10 more Show less

RTL Design Verilog Python Logic Synthesis DFT Physical Design Timing Closure Silicon Debug Power Optimization OCV Effects SOC Verification +6 more Show less

RTL Verilog ASIC Design Micro-architecture Logic Synthesis Timing Analysis C++ Python Perl VLSI Design Computer Architecture DMA Engines Bus Protocols Interconnect Networks Digital Systems Computer Arithmetic +11 more Show less

ASIC Physical Design Logic Synthesis Static Timing Analysis (STA) Logic Equivalence Checking MTBF Analysis Timing Closure DFT Python Perl TCL Make EDA Tools ECO Generation +8 more Show less

ASIC Design RTL Design Verilog System Verilog Python Perl Logic Synthesis Timing Analysis VLSI Computer Architecture VCS Verdi GDB Functional Coverage Assertion-Based Verification Embedded Processors SoC GPU +13 more Show less

RTL NoC Synthesis STA CDC Lint Cache Coherency MESI MOESI Directory-based Coherence Memory Hierarchy Crossbars Arbitration SoC Front-end Synthesis +10 more Show less

Physical Design Python C++ Perl DFT Place and Route Timing Closure Power/Clock/Reset Distribution Agentic AI Chiplet Packaging Algorithm Development +7 more Show less

ASIC Design RTL Design Verilog VHDL Synthesis Timing Analysis CHI CXL PCI-E PERL CAD Tools Hardware-managed Coherency System Level Caches Protocol Bridges Asynchronous Interfaces +10 more Show less

RTL Design Verilog Python Logic Synthesis DFT Physical Design Timing Closure Silicon Debug Power Optimization OCV SOC Verification +6 more Show less

ASIC Design RTL Verilog Micro-architecture VLSI Logic Synthesis Timing Analysis DFT Computer Architecture PCI-Express CXL Python Perl C/C++ CMOS Post-silicon Validation Floor-planning ECO Bus Protocols Interconnect Networks +15 more Show less

Verilog RTL Design ASIC Design VLSI Logic Synthesis Timing Analysis C++ Python Perl Computer Architecture Micro-architecture Digital Systems DMA Engines Bus Protocols Interconnect Networks Caches +11 more Show less

SystemVerilog UVM ASIC Verification Python C/C++ Perl VCS Verdi DFT UPF Machine Learning SoC Functional Coverage Assertion-based Verification GDS +10 more Show less

ASIC Design RTL Micro-architecture SoC DRAM DFI PHY Memory Subsystem Simulators System-on-a-Chip Architecture Research +6 more Show less

RTL NoC SoC Synthesis STA CDC Lint MESI MOESI Directory-based coherence Cache Coherency Memory Hierarchy Crossbars Arbitration Scripting +10 more Show less

RTL ASIC Design NoC Synthesis STA CDC Lint Cache Coherency MESI MOESI Memory Hierarchy Crossbars Arbitration SoC Scripting +10 more Show less

Verilog SystemVerilog RTL Design Synopsys Synthesis Python C++ C Computer Architecture Low Power Design Coverage-based Design Verification OpenGL Vulkan Direct3D ASIC GPU DSP Machine-Learning +12 more Show less

SystemVerilog UVM assertion based verification C++ Python Formal Verification UPF DDR SOC Cache post silicon debug PASIM Power Verification +8 more Show less

SystemVerilog UVM C++ Python Formal Verification assertion based verification UPF DDR SOC Cache post silicon debug PASIM Power Verification +8 more Show less

ASIC Design Verilog system-verilog RTL Design SoC Digital Design Synthesis Timing Closure DFT Clock Domain Crossings AHB AXI Root of Trust Cryptography Error Correction Codes Silicon Testing Microarchitecture +12 more Show less