Senior ASIC Design Engineer - Hardware

Nvidia

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$136,000–$218,500 / yr
Posted
148 days ago

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $190k
This role $177k
$125k most similar roles pay here $236k

This role pays less than 52% of similar roles. Most pay $162,775–$216,250 — the shaded band above. At the midpoint, this role pays about $177k versus about $190k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 563 open roles on FindRole.

Listed pay typically runs $168,000–$264,500 across 556 roles with salary data.

Most-posted roles

View all roles at Nvidia

At a glance

TL;DR · Senior ASIC Design Engineer - Hardware

Apply Now Log in to save

Join NVIDIA’s elite Design team as an ASIC Design Engineer, where you will play a pivotal role in implementing GPU sub-system modules by making critical architectural decisions based on performance requirements. Your daily tasks include developing micro-architecture, coding in RTL, and ensuring designs are fully verified and optimized for synthesis and timing. You’ll collaborate closely with architects, verification teams, and back-end engineers to deliver cutting-edge SoCs and GPUs. Ideal candidates hold a Master’s degree or equivalent experience in Electrical Engineering or Computer Engineering, along with 5+ years of ASIC design expertise, proficiency in Verilog, and knowledge of the entire ASIC design flow. Familiarity with PCI-Express and CXL protocols, as well as Python, Perl, and C/C++, is advantageous for this high-scale computing project.

Skills

Verilog RTL Python Perl C C++ PCI-Express CXL ASIC VLSI Digital systems Computer Architecture CMOS transistors and circuits DFT timing analysis floor-planning ECO bring-up & lab debug arbiters synchronization bus protocols interconnect networks caches

What you'll do

  • Design and implement GPU sub-system modules for leading SoC's and GPU's.
  • Make architectural trade-offs considering features, performance requirements, and system limitations.
  • Develop micro-architecture, write RTL code, and ensure designs are fully verified and timing clean.
  • Support post-silicon validation activities to ensure design integrity.
  • Collaborate with architects, verification teams, synthesis, and back-end teams on tasks.

What we're looking for

  • 5+ years of ASIC design and development experience
  • Masters Degree in Electrical or Computer Engineering required
  • Expertise in micro-architecture and RTL development using Verilog
  • Comprehensive understanding of ASIC design flow processes
  • Experience with PCI-Express (Gen 3+) or CXL protocol beneficial
  • Knowledge of arbiters, synchronization, interconnect networks, caches
  • Proficiency in Python, Perl, and C/C++ programming languages

Related searches

More Senior ASIC Design Engineer jobs Senior ASIC Design Engineer jobs in Santa Clara All jobs at Nvidia

More like this

Similar roles

Senior ASIC Design Engineer

Nvidia

Santa Clara, CA 88 days ago $168,000–$264,500
Verilog RTL C C++ Python Perl VLSI Computer_Architecture Digital_Systems Logic_Synthesis Timing_Analysis
Hybrid
Save

Senior ASIC Design Engineer

Nvidia

Santa Clara, CA 80 days ago $136,000–$218,500
Verilog SystemVerilog Perl Python VCS Verdi GDB Random Stimulus Functional Coverage Assertion-Based Verification Logic Synthesis Timing Analysis Embedded Processors
Save

Senior ASIC Design Engineer

Nvidia

Santa Clara, CA 17 days ago $168,000–$264,500
Verilog System-Verilog RTL ASIC Logic Design Computer Architecture Digital Systems Timing Analysis ECO Post Silicon Debug Arbiters Scheduling Synchronization Bus Protocols Interconnect Networks Switches Virtual Channels
Save

ASIC Design Engineer

Nvidia

Santa Clara, CA 67 days ago $116,000–$189,750
Verilog Perl Python C C++ Kubernetes Terraform CI/CD Docker PostgreSQL Git Jenkins Prometheus Grafana
Save