ASIC Design Engineer

Nvidia

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$116,000–$189,750 / yr
Posted
67 days ago

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $188k
This role $153k
$104k most similar roles pay here $231k

This role pays less than 79% of similar roles. Most pay $158,850–$216,250 — the shaded band above. At the midpoint, this role pays about $153k versus about $188k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 563 open roles on FindRole.

Listed pay typically runs $168,000–$264,500 across 556 roles with salary data.

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View all roles at Nvidia

At a glance

TL;DR · ASIC Design Engineer

As an ASIC Design Engineer at NVIDIA, you will join a cutting-edge engineering team dedicated to developing high-performance SoC and GPU products for applications ranging from consumer graphics to autonomous vehicles. Your daily responsibilities include drafting microarchitecture documents, implementing efficient RTL designs, analyzing architectural trade-offs, and collaborating with architects and verification teams to ensure the delivery of top-tier builds. You will work on various IPs such as time distribution systems and interrupt controllers, and assist in debugging and post-silicon validation activities. Ideal candidates possess a BS/MS degree or equivalent experience in Electrical Engineering, Computer Engineering, or Computer Science, along with 2+ years of RTL design experience, strong Verilog skills, and proficiency in Perl, Python, C/C++, and digital systems/VLSI design.

What you'll do

  • Draft microarchitecture documents for high-performance SoC and GPU products.
  • Implement RTL designs that are area and power-efficient while meeting strict targets.
  • Analyze architectural trade-offs considering performance requirements and constraints.
  • Work on diverse IPs including time distribution systems and interrupt controllers.
  • Collaborate with verification teams to deliver fully verified, synthesis/timing clean builds.

What we're looking for

  • 2+ years of RTL design experience with Verilog.
  • BS/MS in Electrical Engineering, Computer Engineering, or Computer Science.
  • Expertise in micro-architecture and front-end VLSI flows.
  • Proficiency in Perl, Python, C/C++ for scripting and development.
  • Experience with multi-clock domains, asynchronous logic, and interface protocols.
  • Strong debugging, problem-solving, and analytical skills.

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