ASIC Physical Design Engineer, Netlisting

Nvidia

Confirmed live today High trust

Quick summary

Work type: On-site
Location: Santa Clara, CAAustin, TX
Salary: $116,000–$189,750 / yr
Employment: Full-time
Posted: 75 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $183k

This role $153k

$104k $231k

below market most similar roles pay here above market

This role pays less than 71% of similar roles. Most pay $152,875–$214,000 — the blue band above. At the midpoint, this role pays about $153k versus about $183k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · ASIC Physical Design Engineer, Netlisting

Role Posting Log in to save

The ASIC Physical Design Engineer, Netlisting - New College Grad 2026 will join a dynamic team to drive the physical design of high-frequency and low-power CPUs, GPUs, and SoCs. The role focuses on netlist-related aspects including logic synthesis, equivalence checking, asynchronous checking, clock domain crossing checks, and MTBF analysis. The engineer will perform netlist quality checks and assist in ECO generation and implementation at the block, cluster, and full chip levels. Required skills include a Master's or PhD in Electrical or Computer Engineering, knowledge of formal verification from RTL to tapeout, and hardware architecture understanding. Candidates must possess hands-on experience with Synopsys or Cadence EDA tools and proficiency in scripting languages like Perl, TCL, Make, and Python to solve complex hardware design problems.

Skills

ASIC Physical Design Logic Equivalence Checking Formal Verification Logic Synthesis Clock Domain Crossing MTBF Analysis ECO Generation Python Perl TCL Make Synopsys Cadence Hardware Architecture Timing Closure

What you'll do

Drive physical design for high-frequency and low-power CPUs, GPUs, and SoCs at various levels.
Perform logic equivalence checking and formal verification from RTL to tapeout.
Conduct asynchronous checking, including clock domain crossing checks and MTBF analysis.
Execute logic synthesis at the block or full-chip level.
Perform netlist quality checks and help in ECO generation and implementation.
Develop and improve hardware design flows and productivity using programming and scripting languages.
Debug complex hardware issues and solve problems related to timing closure.

What we're looking for

Master's or PhD degree in Electrical or Computer Engineering or equivalent experience.
Knowledge in logic equivalence checking and Formal Verification from RTL to tapeout using industry-standard tools.
Understanding of hardware architecture and hands-on skills in RTL/logic design for timing closure.
Experience in clock-domain-crossing checking and MTBF analysis using EDA tools or in-house tools.
Background in logic synthesis at either block or full-chip level for project execution and/or flow development.
In-depth knowledge of industry standard EDA tools in related fields.
Experience in programming and scripting languages such as Perl, TCL, Make, and Python.
Experience improving workflows and productivity through effective AI utilization (preferred).

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