ASIC Physical Design Engineer, Netlisting

Nvidia

Confirmed live 2 days ago High trust

Quick summary

Work type
On-site
Location
Santa Clara, CAAustin, TX
Salary
$116,000–$189,750 / yr
Posted
29 days ago
Freshness
Confirmed live 2 days ago
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $185k
This role $153k
$104k most similar roles pay here $231k

This role pays less than 73% of similar roles. Most pay $152,875–$216,250 — the shaded band above. At the midpoint, this role pays about $153k versus about $185k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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At a glance

TL;DR · ASIC Physical Design Engineer, Netlisting

Role Posting Log in to save

As an ASIC Physical Design Engineer, Netlisting - New College Grad 2026, you will join a dynamic team focused on the physical design of high-frequency and low-power CPUs, GPUs, and SoCs at block, cluster, and full chip levels. Your daily responsibilities include managing netlist-related tasks such as logic synthesis, equivalence checking, asynchronous checking including clock domain crossing checks and MTBF analysis, and performing netlist quality checks while assisting in ECO generation and implementation. You will utilize industry-standard EDA tools from Synopsys or Cadence alongside scripting languages like Perl, TCL, Make, and Python to solve complex hardware architecture problems. The role specifically addresses the technical challenges of ensuring timing closure and flow development for advanced integrated circuits within the domain of high-performance computing and semiconductor design.

Skills

ASIC Physical Design Logic Synthesis Formal Verification Equivalence Checking RTL Timing Closure Clock Domain Crossing MTBF Analysis Synopsys Cadence Python TCL Perl Make EDA Tools Netlisting ECO Generation

What you'll do

  • Drive physical design for high-frequency and low-power CPUs, GPUs, and SoCs at block and chip levels.
  • Perform netlist-related tasks including logic synthesis and netlist quality checks.
  • Execute equivalence checking and formal verification from RTL to tapeout.
  • Conduct asynchronous checking, including clock domain crossing checks and MTBF analysis.
  • Generate and implement Engineering Change Orders (ECO).
  • Develop and improve design flows and workflows using industry-standard EDA tools.
  • Utilize scripting languages like Python, Perl, or TCL to automate tasks and improve productivity.

What we're looking for

  • Master's or PhD degree in Electrical or Computer Engineering (or equivalent experience).
  • Knowledge of logic equivalence checking and Formal Verification from RTL to tapeout using industry-standard tools.
  • Understanding of hardware architecture and hands-on skills in RTL/logic design for timing closure.
  • Experience in clock-domain-crossing checking and MTBF analysis using EDA or in-house tools.
  • Background in logic synthesis at the block or full-chip level during project execution or flow development.
  • In-depth knowledge of industry standard EDA tools in related fields.
  • Proficiency in programming and scripting languages such as Perl, TCL, Make, and Python.
  • Strong hands-on debugging capability and problem-solving skills.

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