ASIC Physical Design Engineer, Netlisting - New College Grad 2026

Nvidia

Quick summary

Work type
On-site
Location
Santa Clara, CA · Austin, TX
Salary
$116,000–$189,750 / yr
Posted
30 days ago

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $184k
This role $153k
$104k most similar roles pay here $231k

This role pays less than 74% of similar roles. Most pay $152,875–$215,312 — the shaded band above. At the midpoint, this role pays about $153k versus about $184k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 563 open roles on FindRole.

Listed pay typically runs $168,000–$264,500 across 556 roles with salary data.

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At a glance

TL;DR · ASIC Physical Design Engineer, Netlisting - New College Grad 2026

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Join our dynamic team as an ASIC Physical Design Engineer specializing in netlisting, where you will drive the physical design of high-frequency and low-power CPUs, GPUs, and SoCs at various levels. Your daily tasks include equivalence checking, asynchronous checks including clock domain crossing analysis, logic synthesis, and ECO implementation. Ideal candidates hold a Master's or PhD in Electrical or Computer Engineering with expertise in formal verification from RTL to tapeout using industry-standard tools like Synopsys or Cadence. Proficiency in programming languages such as Perl, TCL, Make, and Python is essential, along with hands-on experience in logic synthesis and debugging complex issues. Experience enhancing workflows through AI integration is a significant plus.

Skills

Perl TCL Make Python Synopsys Cadence Logic Synthesis Equivalence Checking Formal Verification Clock Domain Crossing Checks MTBF Analysis RTL Design EDA Tools AI Utilization

What you'll do

  • Drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at various levels focusing on netlist aspects.
  • Perform equivalence checking and asynchronous checks including clock domain crossing analysis for MTBF.
  • Generate and implement ECOs to improve chip designs.
  • Utilize industry-standard tools for logic synthesis and netlist quality checks.
  • Enhance workflows and productivity through effective AI utilization.

What we're looking for

  • Master's or PhD in Electrical/Computer Engineering or equivalent experience.
  • Proven knowledge of logic equivalence checking/Formal Verification using industry-standard tools.
  • Hands-on experience with RTL/logic design for timing closure and hardware architecture understanding.
  • Expertise in clock-domain-crossing checks, MTBF analysis, and logic synthesis at block/full-chip level.
  • Proficiency in programming/scripting languages like Perl, TCL, Make, Python.
  • Strong debugging skills and problem-solving abilities.

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