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PnR Physical Design VLSI STA DRC LVS EMIR Redhawk Totem Voltus Verilog VHDL Python Perl TCL SPICE GDS2 Floor-planning Physical Synthesis +14 more Show less

Dynamic IR EM Noise Signal EM ASIC AMS VLSI Redhawk PrimeRail Voltus PrimeTime Tempus SPICE Scripting Circuit Design Computer Architecture Low Power Techniques +12 more Show less

Static/Dynamic IR EM ESD Gridcheck Redhawk PrimeRail Voltus Innovus Design Compiler PrimeTime Tempus SPICE ASIC VLSI Power Integrity Signoff Low-power Design Digital Systems Computer Architecture +13 more Show less

ASIC Physical Design Place and Route Floorplanning Clock and Power Distribution Global Signal Planning I/O Planning Hard IP Integration STA Design for Yield Multi Vt Database Management P&R Flows Physical Design Verification +9 more Show less

Physical Design Place and Route Floorplanning Clock and Power Distribution Timing Closure Electrical Verification STA Netlist to Tapeout SoC Design +4 more Show less

Physical Design Place and Route Floorplanning Clock and Power Distribution Timing Closure Electrical Verification STA Netlist to Tapeout Chip Architecture +4 more Show less

PnR Physical Design Floorplanning Timing Closure GDS2 Netlist Power Distribution Electrical Verification Signoff Design for Yield Manufacturability Multi-vt +7 more Show less

Physical Design PnR Netlist to GDS2 Floorplanning Clock and Power Distribution Timing Closure Electrical Verification SOC Design Signoff Closure +4 more Show less

PnR Physical Design VLSI STA DRC LVS EMIR Redhawk Totem Voltus Verilog VHDL Python Perl TCL SPICE GDS2 Floor-planning Physical Synthesis +14 more Show less

STA Timing Closure Physical Design Perl TCL SPICE ECO SoC Circuit Modeling OCV Crosstalk +6 more Show less

STA Timing Closure Perl TCL Physical Design ECO SPICE SoC Circuit Modeling OCV Crosstalk Netlist to Tapeout +7 more Show less

Dynamic IR Signal EM Python ASIC AMS VLSI SPICE Circuit Design Computer Architecture Low Power Architecture Tape-out Sign-off Closure +7 more Show less

PnR Physical Design Floorplanning Timing Closure GDS2 Netlist Power Distribution Electrical Verification SOC Design Design for Yield Manufacturability Multi-vt Strategies +7 more Show less

Physical Design PnR Netlist to GDS2 Floorplanning Clock and Power Distribution Timing Closure Electrical Verification SOC Design Signoff Closure +4 more Show less

PnR Physical Design VLSI Verilog VHDL Python Perl TCL SPICE STA DRC LVS EMIR Redhawk Totem Voltus Floor-planning Physical Synthesis GDS2 Netlist +15 more Show less

LVS DRC ANT HVDRC Physical Verification Python Perl Tcl Mentor Calibre Synopsys ICV Layout Design Tapeout Design-for-Manufacturing Design-for-Yield Lithography RDL Design +11 more Show less

Physical Design TCL Python Netlist to GDS PNR Voltage Drop Analysis STA Layout Verification CAD Electrical Analysis DRC Tapeout Automation +8 more Show less

Physical Design TCL Python ASIC Integration Floorplanning Power Distribution Signal Planning I/O Planning Hard IP Integration PNR Voltage Drop Analysis STA Layout Verification DRC CAD Electrical Analysis +11 more Show less

LVS DRC ANT HVDRC ASIC Physical Design Physical Verification Python Perl Tcl Mentor Calibre Synopsys ICV Tapeout Layout Design Design-for-Manufacturing Design-for-Yield Lithography RDL ESD +13 more Show less

LVS DRC ANT Physical Verification Layout Design RTL to GDS Mentor Calibre Synopsys ICV Design-for-Manufacturing Design-for-Yield Lithography Padring Bump RDL Scripting Signoff Closure +11 more Show less