below marketmost similar roles pay hereabove market
This role pays more than
56%
of similar roles. Most pay
$177,250–$231,300
— the blue band above.
At the midpoint, this role pays about
$214k
versus about
$204k
for comparable roles.
Based on 240 similar postings.
Employer
About Apple Inc
Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software
Apple Inc currently has
3497 open roles
on FindRole.
Listed pay typically runs
$174,149–$277,600
across 2702 roles with salary data.
The SoC Physical Design Engineer, Top Level is responsible for implementing complete chip design from netlist to tapeout. Working with the FE team and physical design team, the engineer drives physical aspects early in the design cycle, establishes methodologies, and manages place and route execution. Key responsibilities include setting goals, tracking progress, and resolving design and flow issues. The role requires expertise in ASIC integration, including floorplanning, clock and power distribution, global signal planning, and hard IP integration. Candidates must handle large SoC designs exceeding 20M gates at frequencies over 1GHz using sub 45nm technologies. Required skills include experience with floorplanning tools, P&R flows, global timing verification, physical design verification, database management, and process-related issues like Design for Yield and Manufacturability.
Implement complete chip design from netlist to tapeout.
Drive physical design aspects early in the design cycle by collaborating with the FE team.
Establish methodologies, guidelines, and checklists to streamline physical design work.
Manage place and route tasks, including setting goals, milestones, and planning short-term and long-term work.
Resolve design and flow issues related to physical design and identify potential solutions.
Integrate internal and external IP while specifying physical domain requirements.
Manage database issues and ensure physical convergence for large SoC designs.
Address process-related issues including Design for Yield, Manufacturability, and thermal management.
What we're looking for
Minimum BS degree with 10+ years of experience.
Experience integrating IP from internal and external vendors and specifying physical domain requirements.
Detailed understanding of database management issues.
Experience with floorplanning tools, P&R flows, global timing verification, and physical design verification flows.
Experience with large SoC designs (>20M gates) with frequencies over 1GHz using sub 45nm technologies.
Familiarity with ASIC integration including floorplanning, clock/power distribution, global signal planning, I/O planning, and hard IP integration (preferred).
Experience with SoC issues such as multiple voltage/clock domains, ESD strategies, mixed signal block integration, and package interactions (preferred).
Familiarity with hierarchical design, top-down design, budgeting, timing/physical convergence, and process-related issues like DFM and thermal management (preferred).
Physical Design
Place and Route
Floorplanning
Clock and Power Distribution
Timing Closure
Electrical Verification
STA
Netlist to Tapeout
Chip Architecture