SoC Physical Design Engineer, STA/Timing

Apple Inc

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Quick summary

Work type: On-site
Location: San Jose, CA
Salary: $129,300–$194,700 / yr
Posted: 40 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $206k

This role $162k

$113k $281k

below market most similar roles pay here above market

This role pays less than 85% of similar roles. Most pay $177,250–$233,850 — the blue band above. At the midpoint, this role pays about $162k versus about $206k for comparable roles.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · SoC Physical Design Engineer, STA/Timing

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The SoC Physical Design Engineer, STA/Timing will join the Physical Design team to manage the physical implementation of design partitions from netlist to tapeout for a highly complex SoC using state of the art process technology. The engineer will work with design teams to debug constraints, facilitate logic changes to improve timing, and create timing ECOs for project tapeout. Daily responsibilities include performing deep analysis of timing paths, implementing timing infrastructure, and creating scripts and methodologies for analysis runs. Required skills include experience with STA, noise, crosstalk, and OCV effects. Preferred qualifications include proficiency in Perl and TCL, circuit modeling with SPICE models, and experience with timing closure for large high-performance SoC designs in sub-micron technologies.

Skills

STA Timing Closure Physical Design Perl TCL SPICE ECO SoC Circuit Modeling OCV Crosstalk

What you'll do

Execute physical implementation of design partitions from netlist to tapeout for complex SoCs.
Perform deep analysis of timing paths to identify and resolve critical issues.
Create and implement timing ECOs for project tapeouts.
Develop and maintain scripts and methodologies for analysis and design runs.
Implement timing infrastructure and manage timing closure methodologies.
Debug design constraints and facilitate logic changes to improve timing.
Create technical documentation, guidelines, and specifications for the design process.

What we're looking for

Minimum Bachelor's degree.
Experience with STA.
Experience with noise, crosstalk, and/or OCV effects.
Familiar with timing of large high-performance SoC designs in sub-micron technologies (preferred).
Experience with STA and methodologies for timing closure (preferred).
Familiar with circuit modeling, including SPICE models, and worst-case corner selection (preferred).
Good programming skills with Perl and TCL (preferred).
Experience with large design STA and Timing Closure (preferred).

SoC Physical Design Engineer, STA/Timing

Apple Inc

Austin, TX 40 days ago

STA Timing Closure Physical Design ECO Perl TCL SPICE SoC OCV Crosstalk Circuit Modeling Netlist to Tapeout

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