SoC Physical Design Engineer, Electrical Analysis

What you'll do

• Perform electrical analyses at the block or chip level, including Gridcheck, ESD, IR, and EM.
• Drive EMIR test planning and analysis support throughout the entire chip design cycle.
• Manage sign-off closure for tape-out requirements regarding power integrity.
• Evaluate technology flows and perform bring-up, validation, and qualification for SoC development.
• Automate and debug verification flows for digital VLSI designs.
• Manage project schedules and coordinate cross-functional engineering efforts for SoC product development.

What we're looking for

• Minimum BS degree and 10+ years of relevant industry experience.
• Knowledge of low-power circuit design, computer architecture, and/or digital systems.
• Experience with industrial EDA backend tools including Redhawk, PrimeRail, and Voltus (preferred).
• Experience with ASIC or AMS physical implementation and analysis flow for IP blocks and SoC fullchip (preferred).
• Proficiency in automating and debugging verification flows for digital VLSI design (preferred).
• Experience with Innovus, Design Compiler, PrimeTime, and Tempus (preferred).
• Familiarity with voltage drop budgeting, low-power design techniques, and sign-off criteria for solid-state digital circuit systems (preferred).
• Experience in multiple design tape-outs regarding power integrity signoff and a circuit design background with SPICE experience (preferred).