SoC Physical Design Engineer, PnR

Apple Inc

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: San Jose, CA
Salary: $150,400–$277,600 / yr
Posted: 14 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $203k

This role $214k

$135k most similar roles pay here $293k

This role pays more than 62% of similar roles. Most pay $173,906–$231,300 — the shaded band above. At the midpoint, this role pays about $214k versus about $203k for comparable roles.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 2925 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2305 roles with salary data.

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At a glance

TL;DR · SoC Physical Design Engineer, PnR

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As an SoC Physical Design Engineer, PnR, you will be responsible for the physical implementation of design partitions from netlist to tapeout for highly complex SOCs utilizing innovative process technology. Working closely with the logic design team, you will drive physical aspects early in the design cycle and complete netlist to GDS2 implementations while meeting specific schedule and design goals. Your daily responsibilities include performing timing, physical, and electrical verification to drive signoff closure, as well as identifying and resolving flow issues related to physical design. You will utilize industry standard tools and possess expertise in floorplanning, clock and power distribution, and timing closure. The role involves managing large SOC designs exceeding 20M gates at frequencies over 1GHz using sub 10nm technology nodes to solve complex hardware integration challenges.

Skills

PnR Floorplanning Power Distribution Timing Closure Electrical Verification Netlist SoC Design

What you'll do

Execute netlist to GDS2 implementation for complex SoC partitions.
Drive physical design aspects early in the design cycle with logic teams.
Perform floorplanning, clock distribution, and power distribution for large SoC designs.
Achieve timing closure for high-frequency designs on advanced process nodes.
Complete physical and electrical verification for signoff.
Resolve and improve issues related to physical design flows and methodologies.
Manage implementation tasks while adhering to strict schedule and die size requirements.

What we're looking for

Minimum BS degree and 3+ years of relevant industry experience.
Experience with partition level P&R implementation including floorplanning, clock/power distribution, timing closure, and physical/electrical verification.
Knowledge of physical design construction and analysis flows and methodology.
Experience with industry standard tools and understanding their capabilities and underlying algorithms.
Ability to adhere to stringent schedule and die size requirements (preferred).
Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ (preferred).
Experience with sub 10nm tech nodes (preferred).
Strong communication skills (preferred).