below marketmost similar roles pay hereabove market
This role pays more than
97%
of similar roles. Most pay
$177,250–$229,100
— the blue band above.
At the midpoint, this role pays about
$255k
versus about
$203k
for comparable roles.
Based on 240 similar postings.
Employer
About Apple Inc
Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software
Apple Inc currently has
3497 open roles
on FindRole.
Listed pay typically runs
$174,149–$277,600
across 2702 roles with salary data.
The SoC Physical Design Engineer - Power Delivery joins a team responsible for completing partition place and route from netlist to tapeout, including automation tasks for Apple SOC. The role involves developing features and methodology solutions for a wide range of SOC partitions while ensuring a strong and DRC-clean power grid. Key responsibilities include collaborating multi-functionally with CAD, Physical Verification, Electrical analysis, and PnR teams. The candidate must possess technical expertise in Physical Design automation, specifically using TCL and Python to write maintainable and reusable scripts. Required skills include experience with ASIC integration, floorplanning, clock and power distribution, global signal planning, I/O planning, and hard IP integration. The position requires proficiency with industry standard tools for PNR, Voltage Drop Analysis, STA, and Layout Verification.
Complete partition place and route from netlist to tapeout for Apple SOCs.
Develop automation tasks for Physical Design using TCL and Python.
Design and maintain a DRC-clean power grid for various SOC partitions.
Create features and methodology solutions for use across a wide range of SOC partitions.
Perform floorplanning, clock and power distribution, and global signal planning.
Conduct voltage drop analysis, static timing analysis, and layout verification.
Integrate hard IPs and manage I/O planning for ASIC integration.
What we're looking for
Minimum BS degree and 10+ years of relevant industry experience.
Familiarity with ASIC integration, including floorplanning, clock and power distribution, global signal planning, I/O planning, and hard IP integration.
Experience with scripting and programming to write maintainable and reusable scripts of medium complexity in TCL and/or Python.
Understanding of industry standard tools for PNR, Voltage Drop Analysis, STA, and Layout Verification.
Experience with automation for Physical Design, including block execution (preferred).
Experience with cross-functional collaboration with CAD, Physical Verification, Electrical analysis, and PnR teams (preferred).
Experience with latest technology nodes tapeout (preferred).
Physical Design
ASIC Integration
TCL
Python
Place and Route
Floorplanning
Power Distribution
STA
Layout Verification
Voltage Drop Analysis
DRC
Hard IP Integration
CAD
Electrical Analysis
Physical Design
TCL
Python
ASIC Integration
Floorplanning
Power Distribution
Signal Planning
I/O Planning
Hard IP Integration
PNR
Voltage Drop Analysis
STA
Layout Verification
DRC
Automation
Netlist to Tapeout