SoC Physical Design Engineer, Power Delivery

Apple Inc

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: San Jose, CA
Salary: $184,700–$324,800 / yr
Posted: 58 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $189k

This role $255k

$127k most similar roles pay here $346k

This role pays more than 93% of similar roles. Most pay $160,875–$217,500 — the shaded band above. At the midpoint, this role pays about $255k versus about $189k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

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At a glance

TL;DR · SoC Physical Design Engineer, Power Delivery

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As an SoC Physical Design Engineer - Power Delivery, you will join a team responsible for completing partition place and route from netlist to tapeout, including automation tasks for Apple SOC. You will develop features and methodology solutions used by a wide range of SOC partitions while collaborating multi-functionally with CAD, Physical Verification, Electrical analysis, and PnR teams to ensure a robust, DRC-clean power grid. The role requires expertise in floorplanning, clock and power distribution, global signal planning, I/O planning, and hard IP integration. You will utilize industry standard tools for PNR, Voltage Drop Analysis, STA, and Layout Verification. To succeed, you must possess programming skills to write maintainable scripts in TCL or Python to automate physical design block execution across various advanced technology nodes.

Skills

Physical Design TCL Python ASIC Integration Floorplanning Power Distribution Signal Planning I/O Planning Hard IP Integration Tapeout Voltage Drop Analysis STA Layout Verification DRC CAD Scripting

What you'll do

Execute partition place and route from netlist to tapeout for Apple SoCs.
Develop automation tasks and features using TCL or Python for physical design processes.
Ensure a DRC-clean power grid through collaboration with CAD, Physical Verification, and Electrical analysis teams.
Create methodology solutions and features applicable to a wide range of SoC partitions.
Manage aspects of ASIC integration including floorplanning, clock distribution, and hard IP integration.
Perform voltage drop analysis and static timing analysis (STA) using industry standard tools.
Develop maintainable and reusable scripts for block execution and physical design automation.

What we're looking for

Minimum of a Bachelor's degree and 10+ years of relevant industry experience.
Familiarity with ASIC integration, including floorplanning, clock/power distribution, global signal planning, I/O planning, and hard IP integration.
Proficiency in scripting and programming to write maintainable and reusable code in TCL or Python.
Experience with automation for Physical Design and block execution.
Understanding of industry standard tools for PNR, Voltage Drop Analysis, STA, and Layout Verification.
Ability to collaborate cross-functionally with CAD, Physical Verification, Electrical analysis, and PnR teams.
Experience with tapeouts on the latest technology nodes is preferred.

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