SoC Physical Design Engineer, PnR

Apple Inc

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: San Jose, CA
Salary: $184,700–$324,800 / yr
Posted: 16 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $210k

This role $255k

$130k most similar roles pay here $346k

This role pays more than 92% of similar roles. Most pay $177,250–$241,750 — the shaded band above. At the midpoint, this role pays about $255k versus about $210k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3553 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2740 roles with salary data.

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At a glance

TL;DR · SoC Physical Design Engineer, PnR

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The SoC Physical Design Engineer, PnR is responsible for the physical implementation of design partitions from netlist to tapeout for highly complex SOCs utilizing innovative process technology. Working closely with the logic design team, the engineer drives physical aspects early in the design cycle and manages the full netlist to GDS2 implementation while meeting specific schedule goals. Key responsibilities include timing, physical, and electrical verification, as well as driving signoff closure and optimizing partitions for Power, Performance, and Area. The role requires expertise in floorplanning, clock and power distribution, and multi-vt strategies. Candidates must be proficient with industry standard tools and understand their underlying algorithms to resolve flow issues. The work involves managing complex SOC challenges such as multiple voltage and clock domains and mixed signal block integration within stringent die size requirements.

Skills

PnR Floorplanning Timing Closure Electrical Verification Power Distribution Netlist to GDS2 SOC Design Design for Yield

What you'll do

Execute netlist to GDS2 implementation for complex SoC partitions.
Drive physical design aspects early in the design cycle with logic teams.
Perform timing, physical, and electrical verification to achieve signoff closure.
Optimize PnR partitions to achieve best Power, Performance, and Area results.
Resolve and improve design and flow issues related to physical design.
Manage floorplanning, clock distribution, and power distribution for SoC designs.
Address process-related issues including Design for Yield and Manufacturability.

What we're looking for

Minimum BS degree and 10+ years of relevant industry experience.
Knowledge of partition level P&R implementation including floorplanning, clock/power distribution, timing closure, and verification.
Knowledge of physical design construction and analysis flows and methodology.
Experience with industry standard tools and understanding of their capabilities and underlying algorithms.
Familiarity with SoC issues such as multiple voltage/clock domains and mixed signal block integration.
MS in Electrical, Electronics, or Computer Engineering (preferred).
Experience with large SOC designs (>20M gates) with frequencies exceeding 1GHz (preferred).
Familiarity with process-related design issues like D1Y, manufacturability, multi-vt strategies, and CAD flow experience (preferred).