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PLL FLL Frequency Synthesis System Verilog RTL VCO DCO Jitter Analysis Op-Amps Scripting SOC SerDes +7 more Show less

Analog IC Design ADC DAC Verilog Matlab C Behavioral Modeling ESD Compliance Spectrum Analyzer Oscilloscope Signal Generator Design for Testability Low Noise Design Op-Amps LDOs Switched-Cap Circuits +11 more Show less

SerDes Analog Mixed-Signal Design CMOS FinFET SystemVerilog Matlab Python VerilogAMS PCIe USB MPHY CDR CTLE DFE LDO Primetime Nanotime Scripting +13 more Show less

Cellular Protocols 3GPP Non Access Stratum NAS SIM AS iOS Interfaces NW Protocols Network Simulation Wireless Software Development Electrical Engineering Computer Science +7 more Show less

RF Design ATE Yield Analysis Reliability Engineering DFM I2C PCIe EVM Test VCO Calibration TX/RX Power Calibration RF Packet Test Data Analysis Cpk GRR Firmware PCB Layout Schematics AI ML +14 more Show less

JavaScript TypeScript React Next.js Angular Vue Python Java C++ HTML5 CSS3 Tailwind CSS Material UI Ant Design D3.js Recharts Plotly.js Apache ECharts Chart.js Highcharts React Flow Cytoscape.js Figma LLM APIs System Design Software Architecture +22 more Show less

Digital Hardware Design Schematic Capture PCB Layout FPGA Embedded Processors PCIe DDR3 DDR4 SDRAM JESD UART SPI 1000BASE-T Mentor Graphic’s Git ClearCase Confluence Logic Analyzers BERTs Signal Intelligence Machine Learning Image Processing +17 more Show less

C++ Linux System Verilog ASIC Design FPGA Design RTL Synthesis Clock Tree Optimization Data Structures Algorithms Design Patterns Git LSF JIRA GCC VLSI Design Logic Design +11 more Show less

Risk Management Framework (RMF) CMMC IDS/IPS COMSEC EMSEC OPSEC Network Protocols Splunk ACAS ESS Red Hat Enterprise Linux Windows NIST 800-series DoD STIG Security+ Automation Systems Engineering Lifecycle +12 more Show less

Python C++ PyTorch Tensor Flow Keras ONNX Runtime WinML Linux Android QNX Quantization Computer Vision NLP Generative AI NPU GPU CPU C R Statistics Probability +16 more Show less

ASIC RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Design Verification Scripting Logic Design +4 more Show less

C Python C++ Java Ubuntu Server RHEL SUSE Windows Server ARM64 x86 RISC-V BIOS UEFI BMC Firmware Firmware Validation Test Automation Cloud Edge +12 more Show less

ASIC Design RTL Coding Hardware Architecture LPDDR HBM NoC SRAM Cache Controller x86 ARM Synthesis Timing Closure Physical Design Gate Level Simulation Power Analysis Digital Design ISA Architecture +12 more Show less

ASIC Design RTL Coding Front-end Digital Design Hardware Architecture LPDDR HBM SRAM Cache Controller NoC x86 ARM Synthesis Timing Closure Gate Level Simulation Power Analysis ISA Architecture +11 more Show less

C C++ Assembly RTOS ARM Android JTAG ADB Version Control Digital Signal Processing Digital Image Processing MISRA ASIL ASIC RTL to GDS Flow Virtuoso EDA +12 more Show less

Static Timing Analysis Primetime Fishtail TCM Tcl Perl Python ASIC Design RTL Design Physical Design Power Analysis Clock Domain Crossing Timing Closure Synthesis +9 more Show less

C C++ Assembly Python Java RTOS Zephyr eCos µC/OS FreeRTOS ARMv8 FPGA Pre-silicon Post-silicon Driver Development Interprocessor Communication Firmware Development +12 more Show less

Databricks AWS Terraform Python SQL NoSQL Amazon EKS Delta Lake MLflow Unity Catalog CI/CD GitHub Actions Jenkins Bash Helm OpenTelemetry Hashicorp Vault OPA Sonar Fivetran +15 more Show less

Large Language Models Python JavaScript Java Spring Autogen LangGraph Semantic Kernel AWS GCP Azure RAG Fine-tuning Prompt Engineering Distributed Training Unit Testing Logging Tracing +13 more Show less

Radio Systems RF Wireless Networking MPLS Ethernet TCP/IP Microwave Broadband CCNA CompTIA Radio Propagation System Architecture Frequency Planning Interference Analysis +10 more Show less